counter8.rpt
来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 770 行 · 第 1/4 页
RPT
770 行
Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(2)__n0002(0)_D));
Temp_Maddsub__n0000__n0053(0)/Temp_Maddsub__n0000__n0053(0)_D2 <= ((Qout(3) AND
NOT Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0051(0)/Temp_Maddsub__n0000__n0051(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(3)__n0002(0)_D));
Temp_Maddsub__n0000__n0055(0)/Temp_Maddsub__n0000__n0055(0)_D2 <= ((Qout(4) AND
NOT Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0053(0)/Temp_Maddsub__n0000__n0053(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(4)__n0002(0)_D));
Temp_Maddsub__n0000__n0057(0)/Temp_Maddsub__n0000__n0057(0)_D2 <= ((Qout(5) AND
NOT Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0055(0)/Temp_Maddsub__n0000__n0055(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(5)__n0002(0)_D));
Temp_Maddsub__n0000__n0059(0)/Temp_Maddsub__n0000__n0059(0)_D2 <= ((Qout(6) AND
NOT Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0057(0)/Temp_Maddsub__n0000__n0057(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(6)__n0002(0)_D));
Temp_Maddsub__n0000__n0061(0)/Temp_Maddsub__n0000__n0061(0)_D2 <= ((Qout(7) AND
NOT Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0059(0)/Temp_Maddsub__n0000__n0059(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(7)__n0002(0)_D));
Temp_Maddsub__n0000__n0063(0)/Temp_Maddsub__n0000__n0063(0)_D2 <= ((Qout(8) AND
NOT Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0061(0)/Temp_Maddsub__n0000__n0061(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(8)__n0002(0)_D));
Temp_Maddsub__n0000__n0065(0)/Temp_Maddsub__n0000__n0065(0)_D2 <= ((Qout(9) AND
NOT Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)_D)
OR (
Temp_Maddsub__n0000__n0063(0)/Temp_Maddsub__n0000__n0063(0)_D2 AND
Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)/Temp_Maddsub__n0000_Mxor_Result(9)__n0002(0)_D));
Temp_Maddsub__n0000__n0067(0)/Temp_Maddsub__n0000__n0067(0)_D2 <= ((Qout(10) AND NOT UP)
OR (Qout(10) AND
Temp_Maddsub__n0000__n0065(0)/Temp_Maddsub__n0000__n0065(0)_D2)
OR (NOT UP AND
Temp_Maddsub__n0000__n0065(0)/Temp_Maddsub__n0000__n0065(0)_D2));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 PGND 51 VCC
2 NC 52 Din<7>
3 PGND 53 PGND
4 PGND 54 PGND
5 VCC 55 PGND
6 PGND 56 CLR
7 NC 57 VCC
8 PGND 58 PGND
9 Qout<9> 59 PGND
10 PGND 60 PGND
11 UP 61 PGND
12 Din<5> 62 GND
13 Din<9> 63 Qout<4>
14 Din<1> 64 L
15 PGND 65 PGND
16 PGND 66 PGND
17 Qout<12> 67 Din<4>
18 Qout<11> 68 Qout<5>
19 NC 69 GND
20 PGND 70 PGND
21 GND 71 Qout<3>
22 PGND 72 PGND
23 PGND 73 NC
24 NC 74 CE
25 PGND 75 GND
26 VCC 76 PGND
27 PGND 77 PGND
28 Din<2> 78 Din<6>
29 Din<12> 79 PGND
30 PGND 80 NC
31 GND 81 PGND
32 Din<11> 82 PGND
33 Qout<1> 83 TDO
34 NC 84 GND
35 Din<3> 85 Qout<6>
36 PGND 86 PGND
37 Qout<2> 87 PGND
38 VCC 88 VCC
39 Qout<0> 89 Din<10>
40 PGND 90 Din<0>
41 PGND 91 Qout<7>
42 Din<8> 92 PGND
43 NC 93 PGND
44 GND 94 PGND
45 TDI 95 CCLK
46 NC 96 PGND
47 TMS 97 Qout<8>
48 TCK 98 VCC
49 Qout<10> 99 PGND
50 PGND 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : FPGA
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : STD
Ground on Unused IOs : ON
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : OFF
Pin Feedback : OFF
Input Limit : 36
Pterm Limit : 90
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