counter8.rpt
来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 770 行 · 第 1/4 页
RPT
770 行
cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: counter8 Date: 4- 7-2006, 2:54PM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
32 /72 ( 44%) 116 /360 ( 32%) 13 /72 ( 18%) 31 /72 ( 43%) 81 /144 ( 56%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 18 18 | I/O : 31 35
Output : 13 13 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 31 31
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 13
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 32 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 32 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
Qout<0> 5 6 FB1_16 STD SLOW 39 I/O O RESET
Qout<10> 6 8 FB3_3 STD SLOW 49 I/O O RESET
Qout<11> 6 8 FB1_3 STD SLOW 18 I/O O RESET
Qout<12> 6 9 FB1_8 STD SLOW 17 I/O O RESET
Qout<1> 6 8 FB1_12 STD SLOW 33 I/O O RESET
Qout<2> 6 8 FB3_8 STD SLOW 37 I/O O RESET
Qout<3> 6 8 FB4_3 STD SLOW 71 I/O O RESET
Qout<4> 6 8 FB3_13 STD SLOW 63 I/O O RESET
Qout<5> 6 8 FB4_8 STD SLOW 68 I/O O RESET
Qout<6> 6 8 FB4_13 STD SLOW 85 I/O O RESET
Qout<7> 6 8 FB2_3 STD SLOW 91 I/O O RESET
Qout<8> 6 8 FB2_8 STD SLOW 97 I/O O RESET
Qout<9> 6 8 FB2_14 STD SLOW 9 I/O O RESET
Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D 2 2 FB2_17 STD 12 I/O I
Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D 2 2 FB2_16 STD 10 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D 2 2 FB2_15 STD 11 I/O I
Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D 2 2 FB3_18 STD 59 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D 2 2 FB3_17 STD 58 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D 2 2 FB3_16 STD 65 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D 2 2 FB2_13 STD 8 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D 2 2 FB2_12 STD 6 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D 2 2 FB2_11 STD 4 GTS/I/O (b)
Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 2 3 FB2_10 STD 1 I/O (b)
Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 2 3 FB2_9 STD 99 GSR/I/O (b)
Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 2 3 FB2_7 STD 3 GTS/I/O (b)
Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 2 3 FB3_15 STD 56 I/O I
Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 2 3 FB3_14 STD 55 I/O (b)
Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 2 3 FB3_12 STD 61 I/O (b)
Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 2 3 FB2_6 STD 96 I/O (b)
Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 2 3 FB2_5 STD 95 I/O I
Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2 2 3 FB2_4 STD 93 I/O (b)
Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2 3 3 FB2_18 STD 92 I/O (b)
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CCLK FB2_5 95 I/O I
CE FB4_11 74 I/O I
CLR FB3_15 56 I/O I
Din<0> FB4_17 90 I/O I
Din<10> FB4_15 89 I/O I
Din<11> FB3_2 32 I/O I
Din<12> FB1_15 29 I/O I
Din<1> FB1_5 14 I/O I
Din<2> FB1_10 28 I/O I
Din<3> FB3_5 35 I/O I
Din<4> FB4_5 67 I/O I
Din<5> FB2_17 12 I/O I
Din<6> FB4_14 78 I/O I
Din<7> FB3_11 52 I/O I
Din<8> FB3_9 42 I/O I
Din<9> FB1_2 13 I/O I
L FB4_2 64 I/O I
UP FB2_15 11 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 4 15 15 23 4/0 18
FB2 16 28 28 45 3/0 18
FB3 9 22 22 30 3/0 18
FB4 3 16 16 18 3/0 18
---- ----- ----- -----
32 116 13/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 16 I/O
(unused) 0 0 \/1 4 FB1_2 13 I/O I
Qout<11> 6 1<- 0 0 FB1_3 STD 18 I/O O
(unused) 0 0 0 5 FB1_4 20 I/O
(unused) 0 0 0 5 FB1_5 14 I/O I
(unused) 0 0 0 5 FB1_6 15 I/O
(unused) 0 0 \/1 4 FB1_7 25 I/O (b)
Qout<12> 6 1<- 0 0 FB1_8 STD 17 I/O O
(unused) 0 0 0 5 FB1_9 22 GCK/I/O
(unused) 0 0 0 5 FB1_10 28 I/O I
(unused) 0 0 \/1 4 FB1_11 23 GCK/I/O (b)
Qout<1> 6 1<- 0 0 FB1_12 STD 33 I/O O
(unused) 0 0 0 5 FB1_13 36 I/O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
(unused) 0 0 0 5 FB1_15 29 I/O I
Qout<0> 5 0 0 0 FB1_16 STD 39 I/O O
(unused) 0 0 0 5 FB1_17 30 I/O
(unused) 0 0 0 5 FB1_18 40 I/O
Signals Used by Logic in Function Block
1: CCLK 6: Din<12> 11: Qout<12>
2: CE 7: Din<1> 12: Qout<1>
3: CLR 8: L 13: Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
4: Din<0> 9: Qout<0> 14: Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
5: Din<11> 10: Qout<11> 15: UP
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Qout<11> XXX.X..X.X...XX......................... 8 8
Qout<12> XXX..X.X.XX..XX......................... 9 9
Qout<1> XXX...XXX..XX........................... 8 8
Qout<0> XXXX...XX............................... 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 28/8
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
(unused) 0 0 \/1 4 FB2_2 94 I/O (b)
Qout<7> 6 1<- 0 0 FB2_3 STD 91 I/O O
Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
2 0 0 3 FB2_4 STD 93 I/O (b)
Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2
2 0 0 3 FB2_5 STD 95 I/O I
Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2
2 0 0 3 FB2_6 STD 96 I/O (b)
Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2
2 0 \/1 2 FB2_7 STD 3 GTS/I/O (b)
Qout<8> 6 1<- 0 0 FB2_8 STD 97 I/O O
Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2
2 0 0 3 FB2_9 STD 99 GSR/I/O (b)
Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2
2 0 0 3 FB2_10 STD 1 I/O (b)
Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
2 0 0 3 FB2_11 STD 4 GTS/I/O (b)
Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
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