📄 counttongbu.tan.qmsg

📁 计数器同步异步预置数清零 verilog hdl 编写
💻 QMSG
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 2 -1 0 } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[0\]~reg0 register count\[7\]~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"count\[0\]~reg0\" and destination register \"count\[7\]~reg0\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\]~reg0 1 REG LC5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count\[0\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "" { count[0]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns count\[7\]~reg0 2 REG LC3 4 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count\[7\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "8.000 ns" { count[0]~reg0 count[7]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "8.000 ns" { count[0]~reg0 count[7]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count[0]~reg0 count[7]~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "" { clk } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count\[7\]~reg0 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count\[7\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "0.000 ns" { clk count[7]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[7]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[7]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "" { clk } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count\[0\]~reg0 2 REG LC5 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count\[0\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "0.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[7]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[7]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "8.000 ns" { count[0]~reg0 count[7]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count[0]~reg0 count[7]~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[7]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[7]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "count\[0\]~reg0 load clk 11.000 ns register " "Info: tsu for register \"count\[0\]~reg0\" (data pin = \"load\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns load 1 PIN PIN_81 16 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 16; PIN Node = 'load'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "" { load } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns count\[0\]~reg0 2 REG LC5 11 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count\[0\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "8.000 ns" { load count[0]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "10.000 ns" { load count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { load load~out count[0]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "" { clk } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count\[0\]~reg0 2 REG LC5 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count\[0\]~reg0'" {  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "0.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "counttongbu.v" "" { Text "G:/verilog HDLchengxu 作业/计数器/同步预置清零/counttongbu.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "10.000 ns" { load count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { load load~out count[0]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" "" { Report "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu_cmp.qrpt" Compiler "counttongbu" "UNKNOWN" "V1" "G:/verilog HDLchengxu 作业/计数器/同步预置清零/db/counttongbu.quartus_db" { Floorplan "G:/verilog HDLchengxu 作业/计数器/同步预置清零/" "" "3.000 ns" { clk count[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out count[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
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