counttongbu.tan.rpt

计数器 同步异步预置数清零 verilog hdl 编写

; tsu                                                                 ;
+-------+--------------+------------+------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To            ; To Clock ;
+-------+--------------+------------+------+---------------+----------+
; N/A   ; None         ; 11.000 ns  ; load ; count[0]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[1]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[2]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[3]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[4]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[5]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[6]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; load ; count[7]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[0]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[1]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[2]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[3]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[4]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[5]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[6]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; clr  ; count[7]~reg0 ; clk      ;
+-------+--------------+------------+------+---------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 8.000 ns   ; count[7]~reg0 ; count[7] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[6]~reg0 ; count[6] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[5]~reg0 ; count[5] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[4]~reg0 ; count[4] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[3]~reg0 ; count[3] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[2]~reg0 ; count[2] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[1]~reg0 ; count[1] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; count[0]~reg0 ; count[0] ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; -3.000 ns ; load ; count[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; load ; count[7]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[6]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; clr  ; count[7]~reg0 ; clk      ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 02 10:49:53 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counttongbu -c counttongbu
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "count[0]~reg0" and destination register "count[7]~reg0" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count[7]~reg0'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count[7]~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "count[0]~reg0" (data pin = "load", clock pin = "clk") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 16; PIN Node = 'load'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "count[7]" through register "count[7]~reg0" is 8.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count[7]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'count[7]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'count[7]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "count[0]~reg0" (data pin = "load", clock pin = "clk") is -3.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 16; PIN Node = 'load'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC5; Fanout = 11; REG Node = 'count[0]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jun 02 10:49:54 2006
    Info: Elapsed time: 00:00:02