countyubu.fit.rpt

计数器 同步异步预置数清零 verilog hdl 编写

Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |countyubu                 ; 8          ; 15   ; |countyubu          ;
+----------------------------+------------+------+---------------------+


+-------------------------------------------------------------------------------------------------+
; Control Signals                                                                                 ;
+----------+----------+---------+--------------+--------+----------------------+------------------+
; Name     ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+----------+----------+---------+--------------+--------+----------------------+------------------+
; clk      ; PIN_83   ; 8       ; Clock        ; yes    ; On                   ; --               ;
; clr      ; PIN_1    ; 2       ; Async. clear ; yes    ; On                   ; --               ;
; count~17 ; SEXP3    ; 7       ; Async. clear ; no     ; --                   ; --               ;
; load     ; PIN_81   ; 2       ; Preset       ; no     ; --                   ; --               ;
+----------+----------+---------+--------------+--------+----------------------+------------------+


+---------------------------------------------------------------------+
; Global & Other Fast Signals                                         ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk  ; PIN_83   ; 8       ; On                   ; --               ;
; clr  ; PIN_1    ; 2       ; On                   ; --               ;
+------+----------+---------+----------------------+------------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+---------------+-----------------+
; Name          ; Fan-Out         ;
+---------------+-----------------+
; count[1]~reg0 ; 8               ;
; count[0]~reg0 ; 8               ;
; count[2]~reg0 ; 7               ;
; count~17      ; 7               ;
; count[3]~reg0 ; 6               ;
; count[4]~reg0 ; 5               ;
; count[5]~reg0 ; 4               ;
; count[6]~reg0 ; 3               ;
; load          ; 2               ;
; count[7]~reg0 ; 2               ;
+---------------+-----------------+


+-----------------------------------------------+
; Interconnect Usage Summary                    ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage            ;
+----------------------------+------------------+
; Output enables             ; 0 / 6 ( 0 % )    ;
; PIA buffers                ; 10 / 288 ( 3 % ) ;
; PIAs                       ; 10 / 288 ( 3 % ) ;
+----------------------------+------------------+


+----------------------------------------------------------------------------+
; LAB External Interconnect                                                  ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects  (Average = 1.25) ; Number of LABs  (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0                                            ; 7                           ;
; 1                                            ; 0                           ;
; 2                                            ; 0                           ;
; 3                                            ; 0                           ;
; 4                                            ; 0                           ;
; 5                                            ; 0                           ;
; 6                                            ; 0                           ;
; 7                                            ; 0                           ;
; 8                                            ; 0                           ;
; 9                                            ; 0                           ;
; 10                                           ; 1                           ;
+----------------------------------------------+-----------------------------+


+----------------------------------------------------------------------+
; LAB Macrocells                                                       ;
+----------------------------------------+-----------------------------+
; Number of Macrocells  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0                                      ; 7                           ;
; 1                                      ; 0                           ;
; 2                                      ; 0                           ;
; 3                                      ; 0                           ;
; 4                                      ; 0                           ;
; 5                                      ; 0                           ;
; 6                                      ; 0                           ;
; 7                                      ; 0                           ;
; 8                                      ; 1                           ;
+----------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; Shareable Expander                                                            ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders  (Average = 0.13) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 7                           ;
; 1                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection                                                                                                                                                                                                                                                   ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input                                                                                                                                 ; Output                                                                                                            ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
;  A  ; LC5        ; clk, clr, load                                                                                                                        ; count[0], count[1]~reg0, count[2]~reg0, count[3]~reg0, count[4]~reg0, count[5]~reg0, count[6]~reg0, count[7]~reg0 ;
;  A  ; LC6        ; clk, count[0]~reg0, count[1]~reg0, count~17                                                                                           ; count[1]~reg0, count[1], count[2]~reg0, count[3]~reg0, count[4]~reg0, count[5]~reg0, count[6]~reg0, count[7]~reg0 ;
;  A  ; LC8        ; clk, count[0]~reg0, count[1]~reg0, count[2]~reg0, count~17                                                                            ; count[2]~reg0, count[2], count[3]~reg0, count[4]~reg0, count[5]~reg0, count[6]~reg0, count[7]~reg0                ;
;  A  ; LC11       ; clk, count[2]~reg0, count[0]~reg0, count[1]~reg0, count[3]~reg0, count~17                                                             ; count[3]~reg0, count[3], count[4]~reg0, count[5]~reg0, count[6]~reg0, count[7]~reg0                               ;
;  A  ; LC13       ; clk, count[3]~reg0, count[2]~reg0, count[0]~reg0, count[1]~reg0, count[4]~reg0, count~17                                              ; count[4]~reg0, count[4], count[5]~reg0, count[6]~reg0, count[7]~reg0                                              ;
;  A  ; LC14       ; clk, count[4]~reg0, count[3]~reg0, count[2]~reg0, count[0]~reg0, count[1]~reg0, count[5]~reg0, count~17                               ; count[5]~reg0, count[5], count[6]~reg0, count[7]~reg0                                                             ;
;  A  ; LC16       ; clk, count[5]~reg0, count[4]~reg0, count[3]~reg0, count[2]~reg0, count[0]~reg0, count[1]~reg0, count[6]~reg0, count~17                ; count[6]~reg0, count[6], count[7]~reg0                                                                            ;
;  A  ; LC3        ; clk, count[6]~reg0, count[5]~reg0, count[4]~reg0, count[3]~reg0, count[2]~reg0, count[0]~reg0, count[1]~reg0, count[7]~reg0, count~17 ; count[7]~reg0, count[7]                                                                                           ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 02 11:02:13 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off countyubu -c countyubu
Info: Selected device EPM7128SLC84-15 for design "countyubu"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Jun 02 11:02:13 2006
    Info: Elapsed time: 00:00:01