📄 countyubu.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L9Q is count[0]~reg0 at LC5
A1L9Q_reg_input = VCC;
A1L9Q = TFFE(A1L9Q_reg_input, GLOBAL(clk), GLOBAL(clr), load, );
--A1L11Q is count[1]~reg0 at LC6
A1L11Q_or_out = A1L11Q;
A1L11Q_reg_input = A1L9Q $ A1L11Q_or_out;
A1L11Q = DFFE(A1L11Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L42 is count~17 at SEXP3
A1L42 = EXP(clr & load);
--A1L31Q is count[2]~reg0 at LC8
A1L31Q_p1_out = A1L9Q & A1L11Q;
A1L31Q_or_out = A1L31Q;
A1L31Q_reg_input = A1L31Q_p1_out $ A1L31Q_or_out;
A1L31Q = DFFE(A1L31Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L51Q is count[3]~reg0 at LC11
A1L51Q_p1_out = A1L31Q & A1L9Q & A1L11Q;
A1L51Q_or_out = A1L51Q;
A1L51Q_reg_input = A1L51Q_p1_out $ A1L51Q_or_out;
A1L51Q = DFFE(A1L51Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L71Q is count[4]~reg0 at LC13
A1L71Q_p1_out = A1L51Q & A1L31Q & A1L9Q & A1L11Q;
A1L71Q_or_out = A1L71Q;
A1L71Q_reg_input = A1L71Q_p1_out $ A1L71Q_or_out;
A1L71Q = DFFE(A1L71Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L91Q is count[5]~reg0 at LC14
A1L91Q_p1_out = A1L71Q & A1L51Q & A1L31Q & A1L9Q & A1L11Q;
A1L91Q_or_out = A1L91Q;
A1L91Q_reg_input = A1L91Q_p1_out $ A1L91Q_or_out;
A1L91Q = DFFE(A1L91Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L12Q is count[6]~reg0 at LC16
A1L12Q_p1_out = A1L91Q & A1L71Q & A1L51Q & A1L31Q & A1L9Q & A1L11Q;
A1L12Q_or_out = A1L12Q;
A1L12Q_reg_input = A1L12Q_p1_out $ A1L12Q_or_out;
A1L12Q = DFFE(A1L12Q_reg_input, GLOBAL(clk), !A1L42, , );
--A1L32Q is count[7]~reg0 at LC3
A1L32Q_p1_out = A1L12Q & A1L91Q & A1L71Q & A1L51Q & A1L31Q & A1L9Q & A1L11Q;
A1L32Q_or_out = A1L32Q;
A1L32Q_reg_input = A1L32Q_p1_out $ A1L32Q_or_out;
A1L32Q = DFFE(A1L32Q_reg_input, GLOBAL(clk), !A1L42, , );
--clk is clk at PIN_83
--operation mode is input
clk = INPUT();
--clr is clr at PIN_1
--operation mode is input
clr = INPUT();
--load is load at PIN_81
--operation mode is input
load = INPUT();
--count[0] is count[0] at PIN_11
--operation mode is output
count[0] = OUTPUT(A1L9Q);
--count[1] is count[1] at PIN_10
--operation mode is output
count[1] = OUTPUT(A1L11Q);
--count[2] is count[2] at PIN_9
--operation mode is output
count[2] = OUTPUT(A1L31Q);
--count[3] is count[3] at PIN_8
--operation mode is output
count[3] = OUTPUT(A1L51Q);
--count[4] is count[4] at PIN_6
--operation mode is output
count[4] = OUTPUT(A1L71Q);
--count[5] is count[5] at PIN_5
--operation mode is output
count[5] = OUTPUT(A1L91Q);
--count[6] is count[6] at PIN_4
--operation mode is output
count[6] = OUTPUT(A1L12Q);
--count[7] is count[7] at PIN_12
--operation mode is output
count[7] = OUTPUT(A1L32Q);
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