countyubu.map.rpt

计数器 同步异步预置数清零 verilog hdl 编写

; aglobal50.inc                    ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/aglobal50.inc           ;
; addcore.tdf                      ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Other                  ; d:/program files/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; look_add.tdf                     ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/look_add.tdf            ;
; altshift.tdf                     ; yes             ; Megafunction           ; d:/program files/quartus/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 8                    ;
; Total registers      ; 8                    ;
; I/O pins             ; 11                   ;
; Shareable expanders  ; 1                    ;
; Maximum fan-out node ; count[0]~reg0        ;
; Maximum fan-out      ; 8                    ;
; Total fan-out        ; 62                   ;
; Average fan-out      ; 3.10                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |countyubu                 ; 8          ; 11   ; |countyubu          ;
+----------------------------+------------+------+---------------------+


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 8           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_rnh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/verilog HDLchengxu 作业/计数器/异步预置清零/countyubu.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 02 11:02:06 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off countyubu -c countyubu
Info: Found 1 design units, including 1 entities, in source file countyubu.v
    Info: Found entity 1: countyubu
Info: Elaborating entity "countyubu" for the top level hierarchy
Warning: Verilog HDL assignment warning at countyubu.v(11): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at countyubu.v(12): truncated value with size 32 to match size of target (8)
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 8 buffer(s)
    Info: Ignored 8 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "clr" to global clear signal
Info: Implemented 20 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 8 output pins
    Info: Implemented 8 macrocells
    Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jun 02 11:02:10 2006
    Info: Elapsed time: 00:00:05