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计数器 同步异步预置数清零 verilog hdl 编写

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-- functions, and any output files any of the foregoing 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L5Q is count[0]~reg0
A1L5Q_reg_input = VCC;
A1L5Q = TFFE(A1L5Q_reg_input, GLOBAL(clk), GLOBAL(clr), load, );


--A1L7Q is count[1]~reg0
A1L7Q_or_out = A1L7Q;
A1L7Q_reg_input = A1L5Q $ A1L7Q_or_out;
A1L7Q = DFFE(A1L7Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L02 is count~17
A1L02 = EXP(GLOBAL(clr) & load);


--A1L9Q is count[2]~reg0
A1L9Q_p1_out = A1L5Q & A1L7Q;
A1L9Q_or_out = A1L9Q;
A1L9Q_reg_input = A1L9Q_p1_out $ A1L9Q_or_out;
A1L9Q = DFFE(A1L9Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L11Q is count[3]~reg0
A1L11Q_p1_out = A1L9Q & A1L5Q & A1L7Q;
A1L11Q_or_out = A1L11Q;
A1L11Q_reg_input = A1L11Q_p1_out $ A1L11Q_or_out;
A1L11Q = DFFE(A1L11Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L31Q is count[4]~reg0
A1L31Q_p1_out = A1L11Q & A1L9Q & A1L5Q & A1L7Q;
A1L31Q_or_out = A1L31Q;
A1L31Q_reg_input = A1L31Q_p1_out $ A1L31Q_or_out;
A1L31Q = DFFE(A1L31Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L51Q is count[5]~reg0
A1L51Q_p1_out = A1L31Q & A1L11Q & A1L9Q & A1L5Q & A1L7Q;
A1L51Q_or_out = A1L51Q;
A1L51Q_reg_input = A1L51Q_p1_out $ A1L51Q_or_out;
A1L51Q = DFFE(A1L51Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L71Q is count[6]~reg0
A1L71Q_p1_out = A1L51Q & A1L31Q & A1L11Q & A1L9Q & A1L5Q & A1L7Q;
A1L71Q_or_out = A1L71Q;
A1L71Q_reg_input = A1L71Q_p1_out $ A1L71Q_or_out;
A1L71Q = DFFE(A1L71Q_reg_input, GLOBAL(clk), !A1L02, , );


--A1L91Q is count[7]~reg0
A1L91Q_p1_out = A1L71Q & A1L51Q & A1L31Q & A1L11Q & A1L9Q & A1L5Q & A1L7Q;
A1L91Q_or_out = A1L91Q;
A1L91Q_reg_input = A1L91Q_p1_out $ A1L91Q_or_out;
A1L91Q = DFFE(A1L91Q_reg_input, GLOBAL(clk), !A1L02, , );


--clk is clk
--operation mode is input

clk = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--load is load
--operation mode is input

load = INPUT();


--count[0] is count[0]
--operation mode is output

count[0] = OUTPUT(A1L5Q);


--count[1] is count[1]
--operation mode is output

count[1] = OUTPUT(A1L7Q);


--count[2] is count[2]
--operation mode is output

count[2] = OUTPUT(A1L9Q);


--count[3] is count[3]
--operation mode is output

count[3] = OUTPUT(A1L11Q);


--count[4] is count[4]
--operation mode is output

count[4] = OUTPUT(A1L31Q);


--count[5] is count[5]
--operation mode is output

count[5] = OUTPUT(A1L51Q);


--count[6] is count[6]
--operation mode is output

count[6] = OUTPUT(A1L71Q);


--count[7] is count[7]
--operation mode is output

count[7] = OUTPUT(A1L91Q);