divider.npl

来自「本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.」· NPL 代码 · 共 29 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT Divider
DESIGN divider
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE devider.vhdl
SOURCE compact_divider.vhdl
STIMULUS t_compact.tbw
STIMULUS t_divider.tbw
[STATUS-ALL]
devider.ncdFile=WARNINGS,1152759472
[STRATEGY-LIST]
Normal=True