scan.v

一个电子中的verilog实验源代码。适合verilog初学者学习参考

// **********************************************************************************
// FileName		:scan.v
//
// Discription	:串行扫描控制模块
//
// Date			:
//
// Author		: dandan
// **********************************************************************************
		
module	scan(clk_1000,reset,input1,input2,input3,input4,input5,input6,led_scan,led_bcd);     
input clk_1000,reset;
input [3:0] input1,input2,input3,input4,input5,input6;
output [5:0] led_scan;
output [3:0] led_bcd;

reg [5:0] led_scan;
reg [3:0] led_bcd;

 always @(posedge clk_1000)
 if(reset)
 	begin
 		led_scan<=6'b111_110;
 		led_bcd<=4'b0;
 	end
 else
 	begin
	       case(led_scan) 
	       6'b111_110 :  
	       		begin
		       		led_scan<=6'b111_101;
		       		led_bcd<=input2;                					
		       	end
	       6'b111_101 :  
	       		begin
	       			led_scan<=6'b111_011;        					
	       			led_bcd<=input3;
	       		end
	       6'b111_011 : 
	       		begin
	       			led_scan<=6'b110_111;    
	       			led_bcd<=input4;
	       		end
	       6'b110_111 :  
	       		begin
	       			led_scan<=6'b101_111;
	       			led_bcd<=input5;
	       		end
	       6'b101_111 :  
	       		begin
	       			led_scan<=6'b011_111;
	       			led_bcd<=input6;
	       		end
	       6'b011_111 :  
	       		begin
	       			led_scan<=6'b111_110;
	       			led_bcd<=input1;
	       		end
	       default    :  
	       		begin
	       			led_scan<=6'b111_110;
	       			led_bcd<=input2;
	       		end
    	   endcase 
	end 
endmodule