_primary.vhd

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity o_alarm is
    port(
        clk_1           : in     vl_logic;
        reset           : in     vl_logic;
        minute_count    : in     vl_logic_vector(7 downto 0);
        sec_count       : in     vl_logic_vector(7 downto 0);
        o_light_on      : in     vl_logic;
        o_light         : out    vl_logic
    );
end o_alarm;