v_encode.v

一个用Verilog编写的编帧、解帧及码速匹配的程序

// ****************************************************************************
//FILE NAME       : v_encode.v
//AUTHOR          : baiyang
//RELEASE HISTORY :
//LAST MODIFY TIME:
//FUNCTION        : Frame Data Encode
//NOTE            :
//Reset Strategy  : rst1_n for clk1 domain (data input  port)
//                  rst2_n for clk2 domain (data output port)
//Clock Domain    : Clock Domain Crossing
//                  clk1: clock frequency for data input  port
//                  clk2: clock frequency for data output port
//$Id$
// ***************************************************************************
// &ModuleBeg; @15
module v_encode(
  clk1,
  clk2,
  din,
  dout,
  dout_sync,
  rst1_n,
  rst2_n
);

// &Ports; @16
output          dout;        
output          dout_sync;   
input           clk1;        
input           clk2;        
input           din;         
input           rst1_n;      
input           rst2_n;      

// &Regs; @17
reg     [4 :0]  bit_cnt_1;   
reg     [5 :0]  bit_cnt_2;   
reg     [3 :0]  blk_cnt_1;   
reg     [15:0]  blk_flag;    
reg     [32:0]  data_fifo;   
reg             dout_sync;   
reg     [2 :0]  flm_sync;    
reg             flm_sync_sel; 
reg     [31:0]  rx_data;     
reg     [2 :0]  sync_cnt;    
reg     [6 :0]  sync_data;   
reg     [32:0]  tx_data;     

// &Wires; @18
wire            blk_end;     
wire            blk_irp;     
wire            clk1;        
wire            clk2;        
wire            din;         
wire            dout;        
wire            flm_event;   
wire            flm_irp;     
wire            flm_sync_end; 
wire            rst1_n;      
wire            rst2_n;      


parameter         RESERVED = 1'b0;

//-- ======================================================================= //
//-- >>>>>>>>>>>>>>>>>>>>>>>> Video Encode Source Domain <<<<<<<<<<<<<<<<<<< //
//-- ======================================================================= //

//-- The flag bit of 16 block data is 1010_1110_0100_1xxx (form block 0 to 15) 
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    blk_flag[15:0] <= {RESERVED, RESERVED, RESERVED, 1'b1,
                       4'b0010, 4'b0111, 4'b0101};
  else // circular shift at each block boundary
    blk_flag[15:0] <= blk_irp ? {blk_flag[0], blk_flag[15:1]} :
                                 blk_flag[15:0];
end

//-- Serial data input to Parallel register convert
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    rx_data[31:0] <= 32'd0;
  else
    rx_data[31:0] <= {din, rx_data[31:1]};
end

//-- Insert the flag bit for each block data (32-bit source)
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    begin
      bit_cnt_1[4:0] <= 5'd0; // Count the 32-bit   data for each block
      blk_cnt_1[3:0] <= 4'd0; // Count the 16-block data for one  frame
    end
  else
    begin
      bit_cnt_1[4:0] <= bit_cnt_1[4:0] + 5'd1;
      blk_cnt_1[3:0] <= blk_cnt_1[3:0] + (blk_irp ? 1'b1 : 1'b0);
    end
end
assign blk_irp = (&(bit_cnt_1[4:0]));              // Last  bit   of one block
assign flm_irp = blk_irp & ~(|(blk_cnt_1[3:0])); // First block of current frame

//-- Data FIFO (33-bit to register "one block data + flag bit")
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    data_fifo[32:0] <= 33'd0;
  else
    data_fifo[32:0] <= blk_irp ? {din, rx_data[30:0], blk_flag[0]} :
                                  data_fifo[32:0];
end


//-- ======================================================================= //
//-- >>>>>>>>>>>>>>>>>>>>>>>> Video Encode Output Domain <<<<<<<<<<<<<<<<<<< //
//-- ======================================================================= //

//-- Synchnize the starting of frame
always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    flm_sync[2:0] <= 3'd0;
  else
    flm_sync[2:0] <= {flm_sync[1:0], flm_irp};
end
assign flm_event = !flm_sync[2] & flm_sync[1];

//-- Parallel data to serial Ouput
always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    begin
      tx_data[32:0]  <= 33'd0;
      bit_cnt_2[5:0] <= 6'd0;
    end
  else
    begin
      tx_data[32:0]  <= (flm_event | blk_end) ? data_fifo[32:0] :
                         flm_sync_sel         ? tx_data[32:0] :
                        {tx_data[0], tx_data[32:1]};
      bit_cnt_2[5:0] <= (flm_event | blk_end |
                         flm_sync_sel) ? 6'd0 : (bit_cnt_2[5:0] + 6'd1);
    end
end
assign blk_end = bit_cnt_2[5]; // end of block at bit 33

//-- Frame Sync bits output
always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    begin
      flm_sync_sel   <= 1'b0;
      sync_cnt[2:0]  <= 3'd1;
      sync_data[6:0] <= 7'b010_1101;
    end
  else
    begin
      flm_sync_sel   <= flm_event    ? 1'b1 :
                        flm_sync_end ? 1'b0 : flm_sync_sel;
      sync_cnt[2:0]  <= flm_sync_sel ? (sync_cnt[2:0] + 3'd1) : 1'b1;
      sync_data[6:0] <= flm_sync_sel ? {sync_data[0], sync_data[6:1]} :
                                                      sync_data[6:0];
    end
end
assign flm_sync_end = (&(sync_cnt[2:0]));


//-- ----------------------------------------------------------------------- //
//-- Encoded frame data out
//-- ----------------------------------------------------------------------- //
assign dout = flm_sync_sel ? sync_data[0] : tx_data[0];

always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    dout_sync <= 1'b0; // starting of a frame
  else
    dout_sync <= flm_event;
end

// &ModuleEnd @141
endmodule