v_decode.v

一个用Verilog编写的编帧、解帧及码速匹配的程序

// ****************************************************************************
//FILE NAME       : v_decode.v
//AUTHOR          : xiaobai
//RELEASE HISTORY :
//LAST MODIFY TIME:
//FUNCTION        : Frame Data Decode
//NOTE            :
//Reset Strategy  : rst1_n for clk1 domain (data input  port)
//                  rst2_n for clk2 domain (data output port)
//Clock Domain    : Clock Domain Crossing
//                  clk1: clock frequency for data input  port
//                  clk2: clock frequency for data output port
//$Id$
// ***************************************************************************
// &ModuleBeg; @15
module v_decode(
  clk1,
  clk2,
  din,
  dout,
  dout_sync,
  rst1_n,
  rst2_n
);

// &Ports; @16
output          dout;       
output          dout_sync;  
input           clk1;       
input           clk2;       
input           din;        
input           rst1_n;     
input           rst2_n;     

// &Regs; @17
reg     [4 :0]  bit_cnt_1;  
reg     [4 :0]  bit_cnt_2;  
reg     [3 :0]  blk_cnt_1;  
reg     [1 :0]  d_cs;       
reg     [1 :0]  d_ns;       
reg     [31:0]  data_fifo;  
reg             dout_sync;  
reg     [2 :0]  flm_sync;   
reg     [31:0]  rx_data;    
reg             rx_data_sel; 
reg     [15:0]  rx_flag;    
reg             rx_flag_sel; 
reg     [6 :0]  rx_sync;    
reg             rx_sync_sel; 
reg     [31:0]  tx_data;    

// &Wires; @18
wire            blk_end;    
wire            blk_irp;    
wire            clk1;       
wire            clk2;       
wire            din;        
wire            dout;       
wire            flm_end;    
wire            flm_event;  
wire            rst1_n;     
wire            rst2_n;     
wire            sync_irp;   


//-- State definition for decodeing state machine
parameter         SYNC = 2'd0,
                  FLAG = 2'd1, 
                  DATA = 2'd2;

//-- ======================================================================= //
//-- >>>>>>>>>>>>>>>>>>>>>>>> Video Decode Source Domain <<<<<<<<<<<<<<<<<<< //
//-- ======================================================================= //

//-- current state generation
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    d_cs[1:0] <= SYNC;
  else
    d_cs[1:0] <= d_ns[1:0];
end

//-- next state generation
// &CombBeg; @39
always @( flm_end
       or sync_irp
       or blk_irp
       or d_cs)
begin
  d_ns[1:0]   = d_cs[1:0];
  rx_sync_sel = 1'b0;
  rx_flag_sel = 1'b0;
  rx_data_sel = 1'b0;
  case(d_cs[1:0])
    SYNC:
      begin
        rx_sync_sel = 1'b1;
        d_ns[1:0]   = sync_irp ? FLAG : SYNC;
      end
    FLAG:
      begin
        rx_flag_sel = 1'b1;
        d_ns[1:0]   = DATA;
      end
    DATA:
      begin
        rx_data_sel = 1'b1;
        if(blk_irp)
          d_ns[1:0] = flm_end ? SYNC : FLAG;
        else
          d_ns[1:0] = DATA;
      end
    default: d_ns[1:0] = SYNC;
  endcase
// &CombEnd; @65
end


//-- Serial data input to Parallel register convert
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    begin
      rx_sync[6:0]  <= 7'd0;
      rx_data[31:0] <= 32'd0;
      rx_flag[15:0] <= 16'd0;
    end
  else
    begin
      rx_sync[6:0]  <= rx_sync_sel ? {din, rx_sync[6 :1]} : 7'd0;
      rx_data[31:0] <= rx_data_sel ? {din, rx_data[31:1]} : rx_data[31:0];
      rx_flag[15:0] <= rx_flag_sel ? {din, rx_flag[15:1]} : rx_flag[15:0];
    end
end
assign sync_irp = ({din, rx_sync[6:1]} == 7'b010_1101);

//-- Remove the flag bit for each block data (32-bit source)
//-- And indicate the end of frame
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    begin
      bit_cnt_1[4:0] <= 5'd0; // Count the 32-bit   data for each block
      blk_cnt_1[3:0] <= 4'd0; // Count the 16-block data for one  frame
    end
  else
    begin
      bit_cnt_1[4:0] <= rx_data_sel ? (bit_cnt_1[4:0] + 5'd1) : 5'd0;
      blk_cnt_1[3:0] <= blk_cnt_1[3:0] + (blk_irp ? 1'b1 : 1'b0);
    end
end
assign blk_irp = &(bit_cnt_1[4:0]);              // Last  bit   of one block
assign flm_end = blk_irp & (&(blk_cnt_1[3:0])); // First block of current frame

//-- Data FIFO (33-bit to register "one block data + flag bit")
always @(posedge clk1 or negedge rst1_n)
begin
  if(!rst1_n)
    data_fifo[31:0] <= 31'd0;
  else
    data_fifo[31:0] <= blk_irp ? {din, rx_data[31:1]} : data_fifo[31:0];
end


//-- ======================================================================= //
//-- >>>>>>>>>>>>>>>>>>>>>>>> Video Decode Output Domain <<<<<<<<<<<<<<<<<<< //
//-- ======================================================================= //

//-- Synchnize the starting of frame
always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    flm_sync[2:0] <= 3'd0;
  else
    flm_sync[2:0] <= {flm_sync[1:0], (blk_irp & ~(|blk_cnt_1[3:0]))};
end
assign flm_event = !flm_sync[2] & flm_sync[1];

//-- Parallel data to serial Ouput
always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    begin
      tx_data[31:0]  <= 32'd0;
      bit_cnt_2[4:0] <= 5'd0;
    end
  else
    begin
      tx_data[31:0]  <= (flm_event | blk_end) ? data_fifo[31:0] :
                        {tx_data[0], tx_data[31:1]};
      bit_cnt_2[4:0] <= (flm_event | blk_end) ? 5'd0 : (bit_cnt_2[4:0] + 5'd1);
    end
end
assign blk_end = &(bit_cnt_2[4:0]); // end of block at bit 32

//-- ----------------------------------------------------------------------- //
//-- Decoded frame data out
//-- ----------------------------------------------------------------------- //
assign dout = tx_data[0];

always @(posedge clk2 or negedge rst2_n)
begin
  if(!rst2_n)
    dout_sync <= 1'b0; // starting of a frame
  else
    dout_sync <= flm_event;
end

// &ModuleEnd @158
endmodule