ceshi.map.qmsg

ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(34) " "Warning: VHDL Process Statement warning at ceshi.vhd(34): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "B ceshi.vhd(34) " "Warning: VHDL Process Statement warning at ceshi.vhd(34): signal \"B\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C ceshi.vhd(34) " "Warning: VHDL Process Statement warning at ceshi.vhd(34): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C ceshi.vhd(35) " "Warning: VHDL Process Statement warning at ceshi.vhd(35): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(35) " "Warning: VHDL Process Statement warning at ceshi.vhd(35): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "B ceshi.vhd(35) " "Warning: VHDL Process Statement warning at ceshi.vhd(35): signal \"B\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Y ceshi.vhd(37) " "Warning: VHDL Process Statement warning at ceshi.vhd(37): signal \"Y\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C ceshi.vhd(38) " "Warning: VHDL Process Statement warning at ceshi.vhd(38): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Cin ceshi.vhd(40) " "Warning: VHDL Process Statement warning at ceshi.vhd(40): signal \"Cin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(41) " "Warning: VHDL Process Statement warning at ceshi.vhd(41): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(43) " "Warning: VHDL Process Statement warning at ceshi.vhd(43): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Cin ceshi.vhd(47) " "Warning: VHDL Process Statement warning at ceshi.vhd(47): signal \"Cin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(48) " "Warning: VHDL Process Statement warning at ceshi.vhd(48): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A ceshi.vhd(50) " "Warning: VHDL Process Statement warning at ceshi.vhd(50): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Y ceshi.vhd(18) " "Warning: VHDL Process Statement warning at ceshi.vhd(18): signal or variable \"Y\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Y\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "C ceshi.vhd(18) " "Warning: VHDL Process Statement warning at ceshi.vhd(18): signal or variable \"C\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"C\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "ceshi.vhd" "" { Text "E:/Quartus/ceshi.vhd" 18 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "3 " "Info: Ignored 3 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "3 " "Info: Ignored 3 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "45 " "Info: Implemented 45 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "27 " "Info: Implemented 27 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 36 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 10 19:55:37 2006 " "Info: Processing ended: Wed May 10 19:55:37 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}