ceshi.map.eqn

ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L64 is Y~32
A1L64_p2_out = A[0] & !B[0];
A1L64_p3_out = !A[0] & B[0];
A1L64_or_out = A1L64_p2_out # A1L64_p3_out;
A1L64 = Cin $ A1L64_or_out;


--A1L42 is Mux~2254
A1L42_p0_out = B[0] & !S[0] & A[0];
A1L42_p1_out = Cin & B[0];
A1L42_p2_out = Cin & S[0] & !A[0];
A1L42_p3_out = Cin & !S[0] & A[0];
A1L42_p4_out = B[0] & S[0] & !A[0];
A1L42_or_out = A1L42_p0_out # A1L42_p1_out # A1L42_p2_out # A1L42_p3_out # A1L42_p4_out;
A1L42 = A1L42_or_out;


--A1L24 is Y[0]~55
A1L24_p1_out = A1L64 & !S[1] & !S[2];
A1L24_p2_out = A1L24 & A1L22;
A1L24_p3_out = A1L64 & A1L24;
A1L24_or_out = A1L24_p1_out # A1L24_p2_out # A1L24_p3_out;
A1L24 = A1L24_or_out;


--A1L61 is C[0]~141
A1L61_p1_out = A1L42 & !S[1] & !S[2];
A1L61_p2_out = A1L61 & A1L22;
A1L61_p3_out = A1L42 & A1L61;
A1L61_or_out = A1L61_p1_out # A1L61_p2_out # A1L61_p3_out;
A1L61 = A1L61_or_out;


--A1L74 is Y~34
A1L74_p2_out = A1L61 & !B[1];
A1L74_p3_out = !A1L61 & B[1];
A1L74_or_out = A1L74_p2_out # A1L74_p3_out;
A1L74 = A[1] $ A1L74_or_out;


--A1L72 is Mux~2287
A1L72_p0_out = !S[1] & !S[2] & A1L24;
A1L72_p1_out = A[0] & !Cin & !S[0] & S[1] & !S[2];
A1L72_p2_out = !A[0] & Cin & !S[0] & S[1] & !S[2];
A1L72_p3_out = A[0] & Cin & S[0] & S[1] & !S[2];
A1L72_p4_out = !A[0] & !Cin & S[0] & S[1] & !S[2];
A1L72_or_out = A1L72_p0_out # A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = A1L72_or_out;


--A1L82 is Mux~2288
A1L82_or_out = A[1];
A1L82 = S[0] $ A1L82_or_out;


--A1L52 is Mux~2256
A1L52_p1_out = A1L61 & B[1];
A1L52_p2_out = A1L61 & A1L82;
A1L52_p3_out = B[1] & A1L82;
A1L52_or_out = A1L52_p1_out # A1L52_p2_out # A1L52_p3_out;
A1L52 = A1L52_or_out;


--A1L34 is Y[1]~64
A1L34_p1_out = A1L74 & !S[1] & !S[2];
A1L34_p2_out = A1L34 & A1L22;
A1L34_p3_out = A1L74 & A1L34;
A1L34_or_out = A1L34_p1_out # A1L34_p2_out # A1L34_p3_out;
A1L34 = A1L34_or_out;


--A1L71 is C[1]~145
A1L71_p1_out = A1L52 & !S[1] & !S[2];
A1L71_p2_out = A1L71 & A1L22;
A1L71_p3_out = A1L52 & A1L71;
A1L71_or_out = A1L71_p1_out # A1L71_p2_out # A1L71_p3_out;
A1L71 = A1L71_or_out;


--A1L92 is Mux~2301
A1L92_p0_out = S[1] & S[0] & !A[1] & !A[0] & !Cin;
A1L92_p1_out = S[1] & !S[0] & A[1] & !A[0];
A1L92_p2_out = S[1] & A[1] & A[0] & !Cin;
A1L92_p3_out = S[1] & !S[0] & !A[1] & A[0] & Cin;
A1L92_p4_out = S[1] & S[0] & A[1] & Cin;
A1L92_or_out = A1L92_p0_out # A1L92_p1_out # A1L92_p2_out # A1L92_p3_out # A1L92_p4_out;
A1L92 = A1L92_or_out;


--A1L03 is Mux~2304
A1L03_p1_out = !S[2] & !S[1] & A1L34;
A1L03_p2_out = !S[2] & A1L92;
A1L03_or_out = A1L03_p1_out # A1L03_p2_out;
A1L03 = A1L03_or_out;


--A1L84 is Y~36
A1L84_p2_out = A1L71 & !B[2];
A1L84_p3_out = !A1L71 & B[2];
A1L84_or_out = A1L84_p2_out # A1L84_p3_out;
A1L84 = A[2] $ A1L84_or_out;


--A1L13 is Mux~2305
A1L13_or_out = A[2];
A1L13 = S[0] $ A1L13_or_out;


--A1L62 is Mux~2258
A1L62_p1_out = A1L71 & B[2];
A1L62_p2_out = A1L71 & A1L13;
A1L62_p3_out = B[2] & A1L13;
A1L62_or_out = A1L62_p1_out # A1L62_p2_out # A1L62_p3_out;
A1L62 = A1L62_or_out;


--A1L44 is Y[2]~73
A1L44_p1_out = A1L84 & !S[1] & !S[2];
A1L44_p2_out = A1L44 & A1L22;
A1L44_p3_out = A1L84 & A1L44;
A1L44_or_out = A1L44_p1_out # A1L44_p2_out # A1L44_p3_out;
A1L44 = A1L44_or_out;


--A1L81 is C[2]~149
A1L81_p1_out = A1L62 & !S[1] & !S[2];
A1L81_p2_out = A1L81 & A1L22;
A1L81_p3_out = A1L62 & A1L81;
A1L81_or_out = A1L81_p1_out # A1L81_p2_out # A1L81_p3_out;
A1L81 = A1L81_or_out;


--A1L23 is Mux~2313
A1L23_p2_out = S[1] & !S[0] & Cin & A[1] & A[0];
A1L23_p3_out = S[1] & S[0] & !Cin & !A[1] & !A[0];
A1L23_p4_out = !S[1] & A[2];
A1L23_or_out = A1L23_p2_out # A1L23_p3_out # A1L23_p4_out;
A1L23 = A[2] $ A1L23_or_out;


--A1L33 is Mux~2321
A1L33_p1_out = !S[2] & !S[1] & A1L44;
A1L33_p2_out = !S[2] & A1L23;
A1L33_or_out = A1L33_p1_out # A1L33_p2_out;
A1L33 = A1L33_or_out;


--A1L94 is Y~38
A1L94_p2_out = A1L81 & !B[3];
A1L94_p3_out = !A1L81 & B[3];
A1L94_or_out = A1L94_p2_out # A1L94_p3_out;
A1L94 = A[3] $ A1L94_or_out;


--A1L43 is Mux~2322
A1L43_or_out = A[3];
A1L43 = S[0] $ A1L43_or_out;


--A1L32 is Mux~2252
A1L32_p1_out = A1L81 & B[3];
A1L32_p2_out = A1L81 & A1L43;
A1L32_p3_out = B[3] & A1L43;
A1L32_or_out = A1L32_p1_out # A1L32_p2_out # A1L32_p3_out;
A1L32 = A1L32_or_out;


--A1L54 is Y[3]~82
A1L54_p1_out = A1L94 & !S[1] & !S[2];
A1L54_p2_out = A1L54 & A1L22;
A1L54_p3_out = A1L94 & A1L54;
A1L54_or_out = A1L54_p1_out # A1L54_p2_out # A1L54_p3_out;
A1L54 = A1L54_or_out;


--A1L91 is C[3]~153
A1L91_p1_out = A1L32 & !S[1] & !S[2];
A1L91_p2_out = A1L91 & A1L22;
A1L91_p3_out = A1L32 & A1L91;
A1L91_or_out = A1L91_p1_out # A1L91_p2_out # A1L91_p3_out;
A1L91 = A1L91_or_out;


--A1L53 is Mux~2331
A1L53_p1_out = A1L91 & !S[1] & !S[2];
A1L53_or_out = A1L53_p1_out;
A1L53 = A1L53_or_out;


--A1L63 is Mux~2332
A1L63_p2_out = S[1] & !S[0] & A[1] & Cin & A[2] & A[0];
A1L63_p3_out = S[1] & S[0] & !A[1] & !Cin & !A[2] & !A[0];
A1L63_p4_out = !S[1] & A[3];
A1L63_or_out = A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;
A1L63 = A[3] $ A1L63_or_out;


--A1L73 is Mux~2340
A1L73_p1_out = !S[2] & !S[1] & A1L54;
A1L73_p2_out = !S[2] & A1L63;
A1L73_or_out = A1L73_p1_out # A1L73_p2_out;
A1L73 = A1L73_or_out;


--A1L22 is Mux~2248sexp
A1L22 = EXP(!S[1] & !S[2]);


--A[0] is A[0]
--operation mode is input

A[0] = INPUT();


--A[1] is A[1]
--operation mode is input

A[1] = INPUT();


--A[2] is A[2]
--operation mode is input

A[2] = INPUT();


--A[3] is A[3]
--operation mode is input

A[3] = INPUT();


--B[0] is B[0]
--operation mode is input

B[0] = INPUT();


--B[1] is B[1]
--operation mode is input

B[1] = INPUT();


--B[2] is B[2]
--operation mode is input

B[2] = INPUT();


--B[3] is B[3]
--operation mode is input

B[3] = INPUT();


--Cin is Cin
--operation mode is input

Cin = INPUT();


--S[0] is S[0]
--operation mode is input

S[0] = INPUT();


--S[1] is S[1]
--operation mode is input

S[1] = INPUT();


--S[2] is S[2]
--operation mode is input

S[2] = INPUT();


--BCDout[0] is BCDout[0]
--operation mode is output

BCDout[0] = OUTPUT(A1L72);


--BCDout[1] is BCDout[1]
--operation mode is output

BCDout[1] = OUTPUT(A1L03);


--BCDout[2] is BCDout[2]
--operation mode is output

BCDout[2] = OUTPUT(A1L33);


--BCDout[3] is BCDout[3]
--operation mode is output

BCDout[3] = OUTPUT(A1L73);


--Cout is Cout
--operation mode is output

Cout = OUTPUT(A1L53);