ceshi.vhd

ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- 4 bits 算术单元
entity ceshi is
port
(A:in UNSIGNED (3 downto 0);
 B:in UNSIGNED (3 downto 0);
 Cin:in STD_LOGIC;
 S:in STD_LOGIC_VECTOR (2 downto 0);
 BCDout:out STD_LOGIC_VECTOR (3 downto 0);
 Cout:out STD_LOGIC);
end ceshi;
architecture a of ceshi is
         SIGNAL C,Y: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (S)
BEGIN
    case S is
        when "000" =>  --加法
           Y(0) <= A(0) XOR B(0) XOR Cin;
           C(0) <= (A(0) AND B(0)) OR (B(0) AND Cin) OR (A(0) AND Cin);
           GEN1 : FOR I IN 1 TO 3 LOOP
                    Y(I) <= A(I) XOR B(I) XOR C(I-1);
                    C(I) <= (C(I-1) AND A(I)) OR (C(I-1) AND B(I)) OR (A(I) AND B(I));
           END LOOP;
           BCDout <= Y(3) & Y(2) & Y(1) & Y(0);
           Cout <= C(3);
        when "001" => --减法
           Y(0) <= A(0) XOR B(0) XOR Cin;
           C(0) <= (Cin AND NOT A(0)) OR (Cin AND B(0)) OR (NOT A(0) AND B(0));
           GEN2: FOR I IN 1 TO 3 LOOP
                 Y(I) <= A(I) XOR B(I) XOR C(I-1);
                 C(I) <= (C(I-1) AND NOT A(I)) OR (C(I-1) AND B(I)) OR (NOT A(I) AND B(I));
           END LOOP;
           BCDout <= Y(3) & Y(2) & Y(1) & Y(0);
           Cout <= C(3);
        when "010"  => --传递A+Cin
           IF Cin='0' THEN
              BCDout <= A(3) & A(2) & A(1) & A(0);
           ELSE
              BCDout <= A+1;
           END IF;
              Cout <= '0';
        when "011" => --传递A-Cin;
           IF Cin='1' THEN 
              BCDout <= A(3) & A(2) & A(1) & A(0);
           ELSE
              BCDout <= A-1;
           END IF;
              Cout <='0';
        when others =>
              BCDout <= "0000";
              Cout <= '0';
      END case;
END PROCESS;
end a;