m74148a.fit.summary

采用verilog设计

Flow Status : Successful - Tue Mar 28 09:14:32 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : m74148a
Top-level Entity Name : m74148a
Family : Stratix
Met timing requirements : N/A
Total logic elements : 11 / 10,570 ( < 1 % )
Total pins : 14 / 336 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Final