📄 yuv_data_out.v
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// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME : yuv_data_out.v
// TYPE : parameter
// DEPARTMENT : pudn ASIC
// AUTHOR : Liu Yuxuan
// AUTHOR' EMAIL : liuyuxuan@pudn.com
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0 12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :
// This module is part of the median filter circuit. This file
// alines the YUV signals for output.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------
`resetall
`timescale 1ns/1ps
module yuv_data_out(
clk,
rst_n,
hs,
vs,
hde,
vde,
vde_bypass,
des_data_y,
des_data_uv,
bypass,
ori_data,
des_de,
des_data,
hs_out,
vs_out,
hde_out,
vde_out
);
// Internal Declarations
input clk;
input rst_n;
input hs;
input vs;
input hde;
input vde;
input vde_bypass;
input [7:0] des_data_y;
input [7:0] des_data_uv;
input bypass;
input [15:0] ori_data;
output des_de;
output [15:0] des_data;
output hs_out;
output vs_out;
output hde_out;
output vde_out;
wire clk;
wire rst_n;
wire hs;
wire vs;
wire hde;
wire vde;
wire vde_bypass;
wire [7:0] des_data_y;
wire [7:0] des_data_uv;
wire des_de;
reg [15:0] des_data;
reg hs_out;
reg vs_out;
reg hde_out;
reg vde_out;
// ### Please start your Verilog code here ###
reg vde_bypass_d1;
reg vde_bypass_d2;
reg vde_bypass_d3;
reg vde_bypass_d4;
reg vde_bypass_d5;
reg vde_bypass_d6;
reg vde_bypass_d7;
reg vde_bypass_d8;
reg [15:0] ori_data_d1;
reg [15:0] ori_data_d2;
reg [15:0] ori_data_d3;
reg [15:0] ori_data_d4;
reg [15:0] ori_data_d5;
reg [15:0] ori_data_d6;
reg [15:0] ori_data_d7;
reg [15:0] ori_data_d8;
reg [15:0] ori_data_d9;
reg [15:0] ori_data_d10;
reg [15:0] ori_data_d11;
reg [15:0] ori_data_d12;
reg [15:0] ori_data_d13;
reg [15:0] ori_data_d14;
reg [15:0] ori_data_d15;
reg [15:0] ori_data_d16;
reg [15:0] ori_data_d17;
reg [15:0] ori_data_d18;
reg [15:0] ori_data_d19;
reg [15:0] ori_data_d20;
reg [15:0] ori_data_d21;
reg [15:0] ori_data_d22;
reg [15:0] ori_data_d23;
reg [15:0] ori_data_d24;
//this always block initializes vde_bypass_d* and generates
//correct vde_bypass_d*
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
vde_bypass_d1<=1'b0;
vde_bypass_d2<=1'b0;
vde_bypass_d3<=1'b0;
vde_bypass_d4<=1'b0;
vde_bypass_d5<=1'b0;
vde_bypass_d6<=1'b0;
vde_bypass_d7<=1'b0;
vde_bypass_d8<=1'b0;
end
else
begin
vde_bypass_d1<=vde_bypass;
vde_bypass_d2<=vde_bypass_d1;
vde_bypass_d3<=vde_bypass_d2;
vde_bypass_d4<=vde_bypass_d3;
vde_bypass_d5<=vde_bypass_d4;
vde_bypass_d6<=vde_bypass_d5;
vde_bypass_d7<=vde_bypass_d6;
vde_bypass_d8<=vde_bypass_d7;
end//else if !rst_n
end//always
//this always block initializes ori_data_d* and generates
//correct ori_data_d*
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
ori_data_d1<=8'b0;
ori_data_d2<=8'b0;
ori_data_d3<=8'b0;
ori_data_d4<=8'b0;
ori_data_d5<=8'b0;
ori_data_d6<=8'b0;
ori_data_d7<=8'b0;
ori_data_d8<=8'b0;
ori_data_d9<=8'b0;
ori_data_d10<=8'b0;
ori_data_d11<=8'b0;
ori_data_d12<=8'b0;
ori_data_d13<=8'b0;
ori_data_d14<=8'b0;
ori_data_d15<=8'b0;
ori_data_d16<=8'b0;
ori_data_d17<=8'b0;
ori_data_d18<=8'b0;
ori_data_d19<=8'b0;
ori_data_d20<=8'b0;
ori_data_d21<=8'b0;
ori_data_d22<=8'b0;
ori_data_d23<=8'b0;
ori_data_d24<=8'b0;
end
else
begin
ori_data_d1<=ori_data;
ori_data_d2<=ori_data_d1;
ori_data_d3<=ori_data_d2;
ori_data_d4<=ori_data_d3;
ori_data_d5<=ori_data_d4;
ori_data_d6<=ori_data_d5;
ori_data_d7<=ori_data_d6;
ori_data_d8<=ori_data_d7;
ori_data_d9<=ori_data_d8;
ori_data_d10<=ori_data_d9;
ori_data_d11<=ori_data_d10;
ori_data_d12<=ori_data_d11;
ori_data_d13<=ori_data_d12;
ori_data_d14<=ori_data_d13;
ori_data_d15<=ori_data_d14;
ori_data_d16<=ori_data_d15;
ori_data_d17<=ori_data_d16;
ori_data_d18<=ori_data_d17;
ori_data_d19<=ori_data_d18;
ori_data_d20<=ori_data_d19;
ori_data_d21<=ori_data_d20;
ori_data_d22<=ori_data_d21;
ori_data_d23<=ori_data_d22;
ori_data_d24<=ori_data_d23;
end//else if !rst_n
end//always
assign des_de=vde_out&&hde_out;
//this always block initializes des_data and generates
//correct des_data
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
des_data<=16'b0;
else
begin
if(bypass)
des_data<=ori_data_d24;
else
begin
if(vde && hde)
des_data<={des_data_y,des_data_uv};
else
des_data<=16'b0;
end//else if bypass
end//else if !rst_n
end//always
//this always block initializes hs_out, vs_out and generates
//hs_out, vs_out
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
hs_out<=1'b0;
vs_out<=1'b0;
end
else
begin
hs_out<=hs;
vs_out<=vs;
end//else if !rst_n
end//always
//this always block initializes hde_out, vde_out and generates
//correct hde_out, vde_out
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
hde_out<=1'b0;
vde_out<=1'b0;
end
else
begin
hde_out<=hde;
if(bypass)
vde_out<=vde_bypass_d8;
else
vde_out<=vde;
end//else if !rst_n
end//always
endmodule⌨️ 快捷键说明
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