line_buffers_mdf.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	line_buffers_mdf.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan, Ye Jian, Liu Lizhuang
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 1.0  16 Mar 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Adaptive Weight Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the noise reduction circuit. This file
//            generates line buffers for Y and UV channels.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module line_buffers_mdf(
   clk,
   rst_n,
   wr_en_1,
   wr_en_2,
   wr_addr,
   wr_data_y,
   wr_data_uv,
   rd_addr,
   
   rd_data_y1_reg,
   rd_data_y2_reg,
   rd_data_uv1_reg,
   rd_data_uv2_reg
);


// Internal Declarations

input         clk;
input         rst_n;
input         wr_en_1;
input         wr_en_2;
input  [10:0] wr_addr;
input  [7:0]  wr_data_y;
input  [7:0]  wr_data_uv;
input  [10:0] rd_addr;
   
output [7:0]  rd_data_y1_reg;
output [7:0]  rd_data_y2_reg;
output [7:0]  rd_data_uv1_reg;
output [7:0]  rd_data_uv2_reg;


wire          clk;
wire          rst_n;
wire          wr_en_1;
wire          wr_en_2;
wire   [10:0] wr_addr;
wire   [7:0]  wr_data_y;
wire   [7:0]  wr_data_uv;
wire   [10:0] rd_addr;
   
reg    [7:0]  rd_data_y1_reg;
reg    [7:0]  rd_data_y2_reg;
reg    [7:0]  rd_data_uv1_reg;
reg    [7:0]  rd_data_uv2_reg;

// ### Please start your Verilog code here ###
wire          not_wr_en_1;
wire          not_wr_en_2;
wire   [15:0] rd_data_1;
wire   [15:0] rd_data_2;

assign not_wr_en_1=~wr_en_1;
assign not_wr_en_2=~wr_en_2;

//this always block initializes rd_data_*_reg and generates
//correct rd_data_*_reg for Artisan memory structure
always @(posedge clk or negedge rst_n)
  begin
  	if(!rst_n)
  	  begin
  	  	rd_data_y1_reg<=8'b0;
  	  	rd_data_y2_reg<=8'b0;
  	  	rd_data_uv1_reg<=8'b0;
  	  	rd_data_uv2_reg<=8'b0;
  	  end
  	else
  	  begin
  	  	rd_data_y1_reg<=rd_data_1[15:8];
  	  	rd_data_y2_reg<=rd_data_2[15:8];
  	  	rd_data_uv1_reg<=rd_data_1[7:0];
  	  	rd_data_uv2_reg<=rd_data_2[7:0];
  	  end//else if !rst_n
  end//always

dsram1920x16 line_buffer_1(
   .QA   (),
	 .CLKA (clk),
	 .CENA (1'b0),
	 .WENA (not_wr_en_1),
	 .AA   (wr_addr),
	 .DA   ({wr_data_y,wr_data_uv}),
	 .OENA (1'b0),
	 .QB   (rd_data_1),
	 .CLKB (clk),
	 .CENB (1'b0),
	 .WENB (1'b1),
	 .AB   (rd_addr),
	 .DB   (),
	 .OENB (1'b0)
);

dsram1920x16 line_buffer_2(
   .QA   (),
	 .CLKA (clk),
	 .CENA (1'b0),
	 .WENA (not_wr_en_2),
	 .AA   (wr_addr),
	 .DA   ({wr_data_y,wr_data_uv}),
	 .OENA (1'b0),
	 .QB   (rd_data_2),
	 .CLKB (clk),
	 .CENB (1'b0),
	 .WENB (1'b1),
	 .AB   (rd_addr),
	 .DB   (),
	 .OENB (1'b0)
);

endmodule