rd_ctr_mdf.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	rd_ctr_mdf.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan, Ye Jian, Liu Lizhuang
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the median filter circuit. This file
//            generates the control signals for reading the line buffers.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module rd_ctr_mdf(
   clk,
   rst_n,
   hs,
   vs,
   hde,
   vde,
   extra_vde,
   active_pixel,
   line_switch,
   rd_data_y1,
   rd_data_y2,
   rd_data_uv1,
   rd_data_uv2,
   
   rd_addr,
   mdf_y_a11,
   mdf_y_a12,
   mdf_y_a13,
   mdf_y_a21,
   mdf_y_a22,
   mdf_y_a23,
   mdf_uv_a11,
   mdf_uv_a12,
   mdf_uv_a13,
   mdf_uv_a21,
   mdf_uv_a22,
   mdf_uv_a23,
   hs_out,
   vs_out,
   hde_out,
   vde_1_out,
   vde_2_out
);


// Internal Declarations

input         clk;
input         rst_n;
input         hs;
input         vs;
input         hde;
input         vde;
input         extra_vde;
input  [11:0] active_pixel;
input         line_switch;
input  [7:0]  rd_data_y1;
input  [7:0]  rd_data_y2;
input  [7:0]  rd_data_uv1;
input  [7:0]  rd_data_uv2;

output [10:0] rd_addr;
output [7:0]  mdf_y_a11;
output [7:0]  mdf_y_a12;
output [7:0]  mdf_y_a13;
output [7:0]  mdf_y_a21;
output [7:0]  mdf_y_a22;
output [7:0]  mdf_y_a23;
output [7:0]  mdf_uv_a11;
output [7:0]  mdf_uv_a12;
output [7:0]  mdf_uv_a13;
output [7:0]  mdf_uv_a21;
output [7:0]  mdf_uv_a22;
output [7:0]  mdf_uv_a23;
output        hs_out;
output        vs_out;
output        hde_out;
output        vde_1_out;
output        vde_2_out;


wire        clk;
wire        rst_n;
wire        hs;
wire        vs;
wire        hde;
wire        vde;
wire        extra_vde;
wire [11:0] active_pixel;
wire        line_switch;
wire [7:0]  rd_data_y1;
wire [7:0]  rd_data_y2;
wire [7:0]  rd_data_uv1;
wire [7:0]  rd_data_uv2;

reg  [10:0] rd_addr;
reg  [7:0]  mdf_y_a11;
reg  [7:0]  mdf_y_a12;
reg  [7:0]  mdf_y_a13;
reg  [7:0]  mdf_y_a21;
reg  [7:0]  mdf_y_a22;
reg  [7:0]  mdf_y_a23;
reg  [7:0]  mdf_uv_a11;
reg  [7:0]  mdf_uv_a12;
reg  [7:0]  mdf_uv_a13;
reg  [7:0]  mdf_uv_a21;
reg  [7:0]  mdf_uv_a22;
reg  [7:0]  mdf_uv_a23;
reg         hs_out;
reg         vs_out;
reg         hde_out;
reg         vde_1_out;
reg         vde_2_out;

// ### Please start your Verilog code here ###

reg        hs_pulse;
reg  [7:0] rd_data_y1_d1;
reg  [7:0] rd_data_y1_d2;
reg  [7:0] rd_data_y1_d3;
reg  [7:0] rd_data_y1_d4;
reg  [7:0] rd_data_y2_d1;
reg  [7:0] rd_data_y2_d2;
reg  [7:0] rd_data_y2_d3;
reg  [7:0] rd_data_y2_d4;
reg  [7:0] rd_data_uv1_d1;
reg  [7:0] rd_data_uv1_d2;
reg  [7:0] rd_data_uv1_d3;
reg  [7:0] rd_data_uv1_d4;
reg  [7:0] rd_data_uv2_d1;
reg  [7:0] rd_data_uv2_d2;
reg  [7:0] rd_data_uv2_d3;
reg  [7:0] rd_data_uv2_d4;
reg  [1:0] line_cnt;
reg        rd_start;
reg        hde_rd_start;

reg        hs_d1, hs_d2, hs_d3, hs_d4, hs_d5, hs_d6;
reg        vs_d1, vs_d2, vs_d3, vs_d4, vs_d5, vs_d6;
reg        hde_d1, hde_d2, hde_d3, hde_d4, hde_d5, hde_d6;
reg        vde_1_d1, vde_1_d2, vde_1_d3, vde_1_d4, vde_1_d5, vde_1_d6;

//this always block initializes hs_pulse and generates
//correct hs_pulse
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      hs_pulse<=1'b0;
	  else
	    begin
	    	if(hs && (!hs_d1))
	    	  hs_pulse<=1'b1;
	    	else
	    	  hs_pulse<=1'b0;
      end//else if !rst_n
  end//always

//this always block initializes line_cnt and generates
//correct line_cnt to indicate the third line
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      line_cnt<=2'b0;
	  else
	    begin
	    	if(vs)
	    	  line_cnt<=2'b0;
	    	if(vde && hs_pulse)
	    	  begin
	    	  	if(line_cnt==2'b11)
	    	  	  line_cnt<=2'b11;
	    	  	else
	    	      line_cnt<=line_cnt+2'b1;
	    	  end
	    end//else if !rst_n
  end//always
  
//this always block initializes rd_start and generates
//correct rd_start when the third line comes
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      rd_start<=1'b0;
	  else if(line_cnt==2'b11)
	    rd_start<=1'b1;
	  else
	    rd_start<=1'b0;
  end//always
  
//this always block initializes hde_rd_start and generates
//correct hde_rd_start
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      hde_rd_start<=1'b0;
	  else
	    begin
	      if(vs)
	        hde_rd_start<=1'b0;
        if(line_cnt==2'b10)
          hde_rd_start<=1'b1;
      end//else if !rst_n
  end//always

//this always block initializes rd_addr and generates
//correct rd_addr
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      rd_addr<=11'b0;
	  else
	    begin
	      if(hs_pulse)
	        rd_addr<=11'b0;
	      else if(rd_addr==(active_pixel-1'b1))
	        rd_addr<=rd_addr;
	      else if(hde_rd_start && hde)
	        rd_addr<=rd_addr+11'b1;
	    end//else if !rst_n
  end//always
  
//this always block prepares data for median filter in Y channel
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	rd_data_y1_d1<=8'b0;
      	rd_data_y1_d2<=8'b0;
      	rd_data_y1_d3<=8'b0;
      	rd_data_y1_d4<=8'b0;
      	rd_data_y2_d1<=8'b0;
      	rd_data_y2_d2<=8'b0;
      	rd_data_y2_d3<=8'b0;
      	rd_data_y2_d4<=8'b0;
      end
	  else
	    begin
	    	rd_data_y1_d1<=rd_data_y1;
	    	rd_data_y1_d2<=rd_data_y1_d1;
	    	rd_data_y1_d3<=rd_data_y1_d2;
	    	rd_data_y1_d4<=rd_data_y1_d3;
	    	rd_data_y2_d1<=rd_data_y2;
	    	rd_data_y2_d2<=rd_data_y2_d1;
	    	rd_data_y2_d3<=rd_data_y2_d2;
	    	rd_data_y2_d4<=rd_data_y2_d3;
	    end//else if !rst_n
  end//always
  
//this always block prepares data for median filter in UV channel
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	rd_data_uv1_d1<=8'b0;
      	rd_data_uv1_d2<=8'b0;
      	rd_data_uv1_d3<=8'b0;
      	rd_data_uv1_d4<=8'b0;
      	rd_data_uv2_d1<=8'b0;
      	rd_data_uv2_d2<=8'b0;
      	rd_data_uv2_d3<=8'b0;
      	rd_data_uv2_d4<=8'b0;
      end
	  else
	    begin
	    	rd_data_uv1_d1<=rd_data_uv1;
	    	rd_data_uv1_d2<=rd_data_uv1_d1;
	    	rd_data_uv1_d3<=rd_data_uv1_d2;
	    	rd_data_uv1_d4<=rd_data_uv1_d3;
	    	rd_data_uv2_d1<=rd_data_uv2;
	    	rd_data_uv2_d2<=rd_data_uv2_d1;
	    	rd_data_uv2_d3<=rd_data_uv2_d2;
	    	rd_data_uv2_d4<=rd_data_uv2_d3;
	    end//else if !rst_n
  end//always
  
//this always block initializes mdf_y_a* and generates
//correct mdf_y_a* for median filter
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	mdf_y_a11<=8'b0;
      	mdf_y_a12<=8'b0;
      	mdf_y_a13<=8'b0;
      	mdf_y_a21<=8'b0;
      	mdf_y_a22<=8'b0;
      	mdf_y_a23<=8'b0;
      end
	  else
	    begin
	    	if(!rd_start)//for first line
	    	  begin
	    	  	if(hde_d4&&(!hde_out))//first column
	    	  	  begin
	    	  	  	mdf_y_a11<=rd_data_y1_d2;
	    	  	    mdf_y_a12<=rd_data_y1_d2;
	    	  	    mdf_y_a13<=rd_data_y1_d1;
	    	  	    mdf_y_a21<=rd_data_y1_d2;