comparator_mdf.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// FILE NAME      :	comparator_mdf.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the median filter circuit. This file
//            generates the comparator.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module comparator_mdf(
   clk,
   rst_n,
   filter_sel,
   input_1,
   input_2,
   input_3,
   
   max,
   min,
   median
);


// Internal Declarations

input         clk;
input         rst_n;
input  [1:0]  filter_sel;
input  [7:0]  input_1;
input  [7:0]  input_2;
input  [7:0]  input_3;

output [7:0]  max;
output [7:0]  min;
output [7:0]  median;


wire        clk;
wire        rst_n;
wire [1:0]  filter_sel;
wire [7:0]  input_1;
wire [7:0]  input_2;
wire [7:0]  input_3;

reg  [7:0]  max;
reg  [7:0]  min;
reg  [7:0]  median;

// ### Please start your Verilog code here ###

reg  [7:0]  input_1_d1;
reg  [7:0]  input_2_d1;
reg  [7:0]  input_3_d1, input_3_d2;
reg  [8:0]  diff_1_2;
reg  [8:0]  diff_max;
reg  [8:0]  diff_min;
wire [7:0]  max_1;
wire [7:0]  min_1;
reg  [7:0]  max_1_d1;
reg  [7:0]  min_1_d1;
wire [7:0]  max_tmp;
wire [7:0]  min_tmp;
wire [7:0]  median_tmp;

//this always block initializes input_*_d* and generates
//correct input_*_d*
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        input_1_d1<=8'b0;
        input_2_d1<=8'b0;
        input_3_d1<=8'b0;
        input_3_d2<=8'b0;
      end
	  else
	    begin
	   	  input_1_d1<=input_1;
	   	  input_2_d1<=input_2;
	   	  input_3_d1<=input_3;
	   	  input_3_d2<=input_3_d1;
	    end//else if !rst_n
  end//always

assign max_1=diff_1_2[8]?input_1_d1:input_2_d1;
assign min_1=diff_1_2[8]?input_2_d1:input_1_d1;

//this always block initializes diff_1_2 and generates
//correct diff_1_2 to compare input_1 and input_2
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      diff_1_2<=9'b0;
	  else
	   	diff_1_2<={1'b1,input_1}-{1'b0,input_2};
  end//always

//this always block initializes max_1_d1, min_1_d1 and generates
//correct max_1_d1, min_1_d1
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        max_1_d1<=8'b0;
        min_1_d1<=8'b0;
      end
	  else
	    begin
	   	  max_1_d1<=max_1;
	   	  min_1_d1<=min_1;
	    end//else if !rst_n
  end//always

assign max_tmp=diff_max[8]?max_1_d1:input_3_d2;
assign min_tmp=diff_min[8]?input_3_d2:min_1_d1;
assign median_tmp=(input_3_d2==max_tmp)?max_1_d1:((input_3_d2==min_tmp)?min_1_d1:input_3_d2);

//this always block initializes diff_max, diff_min and generates
//correct diff_max, diff_min
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        diff_max<=9'b0;
        diff_min<=9'b0;
      end
	  else
	    begin
	   	  diff_max<={1'b1,max_1}-{1'b0,input_3_d1};
	   	  diff_min<={1'b1,min_1}-{1'b0,input_3_d1};
	    end//else if !rst_n
  end//always
  
//this always block initializes result and generates
//correct result
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        max<=8'b0;
        min<=8'b0;
        median<=8'b0;
      end
	  else
	    begin
	    	case(filter_sel)
	    	  2'b00:begin
	    	  	max<=max_tmp;
	    	  	min<=min_tmp;
	    	  	median<=median_tmp;
	    	  end
	    	  2'b01:begin
	    	  	max<=max_tmp;
	    	  	min<=min_tmp;
	    	  	median<=max_tmp;
	    	  end
	    	  2'b10:begin
	    	  	max<=max_tmp;
	    	  	min<=min_tmp;
	    	  	median<=min_tmp;
	    	  end
	    	  default:begin
	    	  	max<=8'b0;
	    	  	min<=8'b0;
	    	  	median<=8'b0;
	    	  end
	    	endcase
	    end//else if !rst_n
  end//always

endmodule