📄 drf1024x16.v
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input r_wb;
input xflag;
begin
if (r_wb)
begin
if (valid_address(AAi))
begin
QAi=mem[AAi];
end
else
begin
x_mem;
QAi=wordx;
end
end
else
begin
if (xflag)
begin
QAi=wordx;
end
else
begin
QAi=QAi;
end
end
end
endtask
task write_mem;
input [addr_width-1:0] a;
input [BITS-1:0] d;
begin
casez({valid_address(a)})
1'b0:begin
x_mem;
end
1'b1: begin
mem[a]=d;
end
endcase
end
endtask
task write_mem_x;
input [addr_width-1:0] a;
begin
casez({valid_address(a)})
1'b0:begin
x_mem;
end
1'b1: begin
mem[a]=wordx;
end
endcase
end
endtask
task x_mem;
integer n;
begin
for (n=0; n<word_depth; n=n+1)
mem[n]=wordx;
end
endtask
function valid_address;
input [addr_width-1:0] a;
begin
valid_address = (^(a) !== 1'bx);
end
endfunction
buf (QA[0], _QA[0]);
buf (QA[1], _QA[1]);
buf (QA[2], _QA[2]);
buf (QA[3], _QA[3]);
buf (QA[4], _QA[4]);
buf (QA[5], _QA[5]);
buf (QA[6], _QA[6]);
buf (QA[7], _QA[7]);
buf (QA[8], _QA[8]);
buf (QA[9], _QA[9]);
buf (QA[10], _QA[10]);
buf (QA[11], _QA[11]);
buf (QA[12], _QA[12]);
buf (QA[13], _QA[13]);
buf (QA[14], _QA[14]);
buf (QA[15], _QA[15]);
buf (_AA[0], AA[0]);
buf (_AA[1], AA[1]);
buf (_AA[2], AA[2]);
buf (_AA[3], AA[3]);
buf (_AA[4], AA[4]);
buf (_AA[5], AA[5]);
buf (_AA[6], AA[6]);
buf (_AA[7], AA[7]);
buf (_AA[8], AA[8]);
buf (_AA[9], AA[9]);
buf (_CLKA, CLKA);
buf (_CENA, CENA);
buf (_DB[0], DB[0]);
buf (_DB[1], DB[1]);
buf (_DB[2], DB[2]);
buf (_DB[3], DB[3]);
buf (_DB[4], DB[4]);
buf (_DB[5], DB[5]);
buf (_DB[6], DB[6]);
buf (_DB[7], DB[7]);
buf (_DB[8], DB[8]);
buf (_DB[9], DB[9]);
buf (_DB[10], DB[10]);
buf (_DB[11], DB[11]);
buf (_DB[12], DB[12]);
buf (_DB[13], DB[13]);
buf (_DB[14], DB[14]);
buf (_DB[15], DB[15]);
buf (_AB[0], AB[0]);
buf (_AB[1], AB[1]);
buf (_AB[2], AB[2]);
buf (_AB[3], AB[3]);
buf (_AB[4], AB[4]);
buf (_AB[5], AB[5]);
buf (_AB[6], AB[6]);
buf (_AB[7], AB[7]);
buf (_AB[8], AB[8]);
buf (_AB[9], AB[9]);
buf (_CLKB, CLKB);
buf (_CENB, CENB);
assign re_flagA = !(_CENA);
assign _QA = QAi;
assign re_flagB = !(_CENB);
assign contA_flag =
(_AA === ABi) &&
(_CENA !== 1'b1) &&
(CENBi !== 1'b1);
assign contB_flag =
(_AB === AAi) &&
(_CENB !== 1'b1) &&
(CENAi !== 1'b1);
assign cont_flag =
(_AB === _AA) &&
(_CENB !== 1'b1) &&
(_CENA !== 1'b1);
always @(
NOT_AA0 or
NOT_AA1 or
NOT_AA2 or
NOT_AA3 or
NOT_AA4 or
NOT_AA5 or
NOT_AA6 or
NOT_AA7 or
NOT_AA8 or
NOT_AA9 or
NOT_CENA or
NOT_CONTA or
NOT_CLKA_PER or
NOT_CLKA_MINH or
NOT_CLKA_MINL
)
begin
if ((NOT_CLKA_PER!==LAST_NOT_CLKA_PER) ||
(NOT_CLKA_MINH!==LAST_NOT_CLKA_MINH) ||
(NOT_CLKA_MINL!==LAST_NOT_CLKA_MINL))
begin
if (CENAi !== 1'b1)
begin
read_memA(0,1);
end
end
else
begin
update_Anotifier_buses;
x_Ainputs;
update_Alogic;
if (NOT_CONTA!==LAST_NOT_CONTA)
begin
contentionA;
end
else
begin
mem_cycleA;
end
end
update_Alast_notifiers;
end
always @(
NOT_AB0 or
NOT_AB1 or
NOT_AB2 or
NOT_AB3 or
NOT_AB4 or
NOT_AB5 or
NOT_AB6 or
NOT_AB7 or
NOT_AB8 or
NOT_AB9 or
NOT_DB0 or
NOT_DB1 or
NOT_DB2 or
NOT_DB3 or
NOT_DB4 or
NOT_DB5 or
NOT_DB6 or
NOT_DB7 or
NOT_DB8 or
NOT_DB9 or
NOT_DB10 or
NOT_DB11 or
NOT_DB12 or
NOT_DB13 or
NOT_DB14 or
NOT_DB15 or
NOT_CENB or
NOT_CONTB or
NOT_CLKB_PER or
NOT_CLKB_MINH or
NOT_CLKB_MINL
)
begin
if ((NOT_CLKB_PER!==LAST_NOT_CLKB_PER) ||
(NOT_CLKB_MINH!==LAST_NOT_CLKB_MINH) ||
(NOT_CLKB_MINL!==LAST_NOT_CLKB_MINL))
begin
if (CENBi !== 1'b1)
begin
x_mem;
read_memA(0,1);
end
end
else
begin
update_Bnotifier_buses;
x_Binputs;
update_Blogic;
if (NOT_CONTB!==LAST_NOT_CONTB)
begin
contentionB;
end
else
begin
mem_cycleB;
end
end
update_Blast_notifiers;
end
always @( _CLKA )
begin
casez({LAST_CLKA,_CLKA})
2'b01: begin
latch_Ainputs;
update_Alogic;
mem_cycleA;
end
2'b10,
2'bx?,
2'b00,
2'b11: ;
2'b?x: begin
x_mem;
read_memA(0,1);
end
endcase
LAST_CLKA = _CLKA;
end
always @( _CLKB )
begin
casez({LAST_CLKB,_CLKB})
2'b01: begin
latch_Binputs;
update_Blogic;
mem_cycleB;
end
2'b10,
2'bx?,
2'b00,
2'b11: ;
2'b?x: begin
x_mem;
end
endcase
LAST_CLKB = _CLKB;
end
/*
// turn off when simulation
specify
$setuphold(posedge CLKB &&& re_flagB, posedge DB[0], 1.000, 0.500, NOT_DB0);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[0], 1.000, 0.500, NOT_DB0);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[1], 1.000, 0.500, NOT_DB1);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[1], 1.000, 0.500, NOT_DB1);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[2], 1.000, 0.500, NOT_DB2);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[2], 1.000, 0.500, NOT_DB2);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[3], 1.000, 0.500, NOT_DB3);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[3], 1.000, 0.500, NOT_DB3);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[4], 1.000, 0.500, NOT_DB4);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[4], 1.000, 0.500, NOT_DB4);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[5], 1.000, 0.500, NOT_DB5);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[5], 1.000, 0.500, NOT_DB5);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[6], 1.000, 0.500, NOT_DB6);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[6], 1.000, 0.500, NOT_DB6);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[7], 1.000, 0.500, NOT_DB7);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[7], 1.000, 0.500, NOT_DB7);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[8], 1.000, 0.500, NOT_DB8);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[8], 1.000, 0.500, NOT_DB8);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[9], 1.000, 0.500, NOT_DB9);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[9], 1.000, 0.500, NOT_DB9);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[10], 1.000, 0.500, NOT_DB10);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[10], 1.000, 0.500, NOT_DB10);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[11], 1.000, 0.500, NOT_DB11);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[11], 1.000, 0.500, NOT_DB11);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[12], 1.000, 0.500, NOT_DB12);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[12], 1.000, 0.500, NOT_DB12);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[13], 1.000, 0.500, NOT_DB13);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[13], 1.000, 0.500, NOT_DB13);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[14], 1.000, 0.500, NOT_DB14);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[14], 1.000, 0.500, NOT_DB14);
$setuphold(posedge CLKB &&& re_flagB, posedge DB[15], 1.000, 0.500, NOT_DB15);
$setuphold(posedge CLKB &&& re_flagB, negedge DB[15], 1.000, 0.500, NOT_DB15);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[0], 1.000, 0.500, NOT_AB0);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[0], 1.000, 0.500, NOT_AB0);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[1], 1.000, 0.500, NOT_AB1);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[1], 1.000, 0.500, NOT_AB1);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[2], 1.000, 0.500, NOT_AB2);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[2], 1.000, 0.500, NOT_AB2);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[3], 1.000, 0.500, NOT_AB3);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[3], 1.000, 0.500, NOT_AB3);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[4], 1.000, 0.500, NOT_AB4);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[4], 1.000, 0.500, NOT_AB4);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[5], 1.000, 0.500, NOT_AB5);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[5], 1.000, 0.500, NOT_AB5);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[6], 1.000, 0.500, NOT_AB6);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[6], 1.000, 0.500, NOT_AB6);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[7], 1.000, 0.500, NOT_AB7);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[7], 1.000, 0.500, NOT_AB7);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[8], 1.000, 0.500, NOT_AB8);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[8], 1.000, 0.500, NOT_AB8);
$setuphold(posedge CLKB &&& re_flagB, posedge AB[9], 1.000, 0.500, NOT_AB9);
$setuphold(posedge CLKB &&& re_flagB, negedge AB[9], 1.000, 0.500, NOT_AB9);
$setuphold(posedge CLKB, posedge CENB, 1.000, 0.500, NOT_CENB);
$setuphold(posedge CLKB, negedge CENB, 1.000, 0.500, NOT_CENB);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[0], 1.000, 0.500, NOT_AA0);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[0], 1.000, 0.500, NOT_AA0);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[1], 1.000, 0.500, NOT_AA1);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[1], 1.000, 0.500, NOT_AA1);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[2], 1.000, 0.500, NOT_AA2);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[2], 1.000, 0.500, NOT_AA2);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[3], 1.000, 0.500, NOT_AA3);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[3], 1.000, 0.500, NOT_AA3);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[4], 1.000, 0.500, NOT_AA4);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[4], 1.000, 0.500, NOT_AA4);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[5], 1.000, 0.500, NOT_AA5);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[5], 1.000, 0.500, NOT_AA5);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[6], 1.000, 0.500, NOT_AA6);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[6], 1.000, 0.500, NOT_AA6);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[7], 1.000, 0.500, NOT_AA7);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[7], 1.000, 0.500, NOT_AA7);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[8], 1.000, 0.500, NOT_AA8);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[8], 1.000, 0.500, NOT_AA8);
$setuphold(posedge CLKA &&& re_flagA, posedge AA[9], 1.000, 0.500, NOT_AA9);
$setuphold(posedge CLKA &&& re_flagA, negedge AA[9], 1.000, 0.500, NOT_AA9);
$setuphold(posedge CLKA, posedge CENA, 1.000, 0.500, NOT_CENA);
$setuphold(posedge CLKA, negedge CENA, 1.000, 0.500, NOT_CENA);
$period(posedge CLKA, 3.000, NOT_CLKA_PER);
$width(posedge CLKA, 1.000, 0, NOT_CLKA_MINH);
$width(negedge CLKA, 1.000, 0, NOT_CLKA_MINL);
$period(posedge CLKB, 3.000, NOT_CLKB_PER);
$width(posedge CLKB, 1.000, 0, NOT_CLKB_MINH);
$width(negedge CLKB, 1.000, 0, NOT_CLKB_MINL);
$setup(posedge CLKA, posedge CLKB &&& contB_flag, 3.000, NOT_CONTB);
$setup(posedge CLKB, posedge CLKA &&& contA_flag, 3.000, NOT_CONTA);
$hold(posedge CLKA, posedge CLKB &&& cont_flag, 0.001, NOT_CONTB);
(CLKA => QA[0]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[1]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[2]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[3]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[4]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[5]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[6]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[7]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[8]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[9]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[10]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[11]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[12]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[13]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[14]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[15]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
endspecify
*/
endmodule
`endcelldefine
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