wr_ctr_mdf.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	wr_ctr_mdf.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan, Ye Jian, Liu Lizhuang
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the midian filter circuit. This file
//            generates the control signals for writing the line buffers.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module wr_ctr_mdf(
   clk,
   rst_n,
   hs,
   vs,
   hde,
   vde,
   extra_vde,
   data_in_y,
   data_in_uv,
   
   line_switch,
   wr_en_1,
   wr_en_2,
   wr_addr,
   wr_data_y,
   wr_data_uv,
   hs_out,
   vs_out,
   hde_out,
   vde_out
);


// Internal Declarations

input         clk;
input         rst_n;
input         hs;
input         vs;
input         hde;
input         vde;
input         extra_vde;
input  [7:0]  data_in_y;
input  [7:0]  data_in_uv;

output        line_switch;
output        wr_en_1;
output        wr_en_2;
output [10:0] wr_addr;
output [7:0]  wr_data_y;
output [7:0]  wr_data_uv;
output        hs_out;
output        vs_out;
output        hde_out;
output        vde_out;


wire        clk;
wire        rst_n;
wire        hs;
wire        vs;
wire        hde;
wire        vde;
wire [7:0]  data_in_y;
wire [7:0]  data_in_uv;

reg         line_switch;
reg         wr_en_1;
reg         wr_en_2;
reg  [10:0] wr_addr;
reg  [7:0]  wr_data_y;
reg  [7:0]  wr_data_uv;
reg         hs_out;
reg         vs_out;
reg         hde_out;
reg         vde_out;

// ### Please start your Verilog code here ###

reg         hs_pulse;

//this always block initializes hs_pulse and generates
//correct hs_pulse
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      hs_pulse<=1'b0;
	  else
	    begin
	    	if(hs && (!hs_out))
	    	  hs_pulse<=1'b1;
	    	else
	    	  hs_pulse<=1'b0;
      end//else if !rst_n
  end//always

//this always block initializes line_switch and generates
//correct line_switch
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      line_switch<=1'b0;
	  else
	    begin
	    	if(vs)
	    	  line_switch<=1'b0;
        if(extra_vde && hs_pulse)
          line_switch<=~line_switch;
      end//else if !rst_n
  end//always

//this always block initializes wr_en_1, wr_en_2 and generates
//correct wr_en_1, wr_en_2
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        wr_en_1<=1'b0;
        wr_en_2<=1'b0;
      end
	  else
      begin
      	if(vde)
      	  begin
      	    if(line_switch)
      	      begin
      	        wr_en_1<=hde;
      	        wr_en_2<=1'b0;
      	      end
      	    else
      	      begin
      	      	wr_en_1<=1'b0;
      	        wr_en_2<=hde;
      	      end
      	  end//if vde
      	else
      	  begin
      	  	wr_en_1<=1'b0;
      	  	wr_en_2<=1'b0;
      	  end
      end//else if !rst_n
  end//always
  
//this always block initializes wr_addr and generates
//correct wr_addr
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      wr_addr<=11'b0;
	  else
      begin
      	if(hs_pulse)
     	    wr_addr<=11'b0;
      	else
      	  if(vde && hde_out)
      	    wr_addr<=wr_addr+11'b1;
      end//else if !rst_n
  end//always
  
//this always block initializes wr_data_y, wr_data_uv and generates
//correct wr_data_y, wr_data_uv
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        wr_data_y<=8'b0;
        wr_data_uv<=8'b0;
      end
	  else
      begin
      	if(vde && hde)
      	  begin
      	    wr_data_y<=data_in_y;
      	    wr_data_uv<=data_in_uv;
      	  end
      	else
      	  begin
      	  	wr_data_y<=8'b0;
      	    wr_data_uv<=8'b0;
      	  end
      end//else if !rst_n
  end//always

//this always block initializes hs_out, vs_out and generates
//hs_out, vs_out
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        hs_out<=1'b0;
		    vs_out<=1'b0;
	    end
	  else
	    begin
        hs_out<=hs;
        vs_out<=vs;
      end//else if !rst_n
  end//always
  
//this always block initializes hde_out, vde_out and generates
//correct hde_out, vde_out
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        hde_out<=1'b0;
        vde_out<=1'b0;
      end
    else
      begin
        hde_out<=hde;
        vde_out<=vde;
      end//else if !rst_n
  end//always

endmodule