dsram1920x16.v

3x3中值滤波 verilog

//
//      CONFIDENTIAL AND PROPRIETARY SOFTWARE/DATA OF ARTISAN COMPONENTS, INC.
//      
//      Copyright (c) 2004 Artisan Components, Inc.  All Rights Reserved.
//      
//      Use of this Software/Data is subject to the terms and conditions of
//      the applicable license agreement between Artisan Components, Inc. and
//      SMIC.  In addition, this Software/Data
//      is protected by copyright law and international treaties.
//      
//      The copyright notice(s) in this Software/Data does not indicate actual
//      or intended publication of this Software/Data.
//      name:			SRAM-DP-HS SRAM Generator
//           			SMIC 0.18um Logic018 Process
//      version:		2003Q2V1
//      comment:		
//      configuration:	 -instname dsram1920x16 -words 1920 -bits 16 -frequency 166 -ring_width 2 -mux 16 -drive 12 -write_mask off -wp_size 8 -top_layer met5 -power_type rings -horiz met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname on -diodes on -inside_ring_type GND
//
//      Verilog model for Synchronous Dual-Port Ram
//
//      Instance Name:  dsram1920x16
//      Words:          1920
//      Word Width:     16
//      Pipeline:       No
//
//      Creation Date:  2004-07-10 02:35:11Z
//      Version: 	2003Q2V1
//
//      Verified With: Cadence Verilog-XL
//
//      Modeling Assumptions: This model supports full gate level simulation
//          including proper x-handling and timing check behavior.  Unit
//          delay timing is included in the model. Back-annotation of SDF
//          (v2.1) is supported.  SDF can be created utilyzing the delay
//          calculation views provided with this generator and supported
//          delay calculators.  All buses are modeled [MSB:LSB].  All 
//          ports are padded with Verilog primitives.
//
//      Modeling Limitations: The output hold function has been deleted
//          completely from this model.  Most Verilog simulators are 
//          incapable of scheduling more than 1 event on the rising 
//          edge of clock.  Therefore, it is impossible to model
//          the output hold (to x) action correctly.  It is necessary
//          to run static path timing tools using Artisan supplied
//          timing models to insure that the output hold time is
//          sufficient enough to not violate hold time constraints
//          of downstream flip-flops.
//
//      Known Bugs: None.
//
//      Known Work Arounds: N/A
//
`timescale 1 ns/1 ps
module dsram1920x16 (
   QA,
   CLKA,
   CENA,
   WENA,
   AA,
   DA,
   OENA,
   QB,
   CLKB,
   CENB,
   WENB,
   AB,
   DB,
   OENB
);
   parameter		   BITS = 16;
   parameter		   word_depth = 1920;
   parameter		   addr_width = 11;
   parameter		   wordx = {BITS{1'bx}};
   parameter		   addrx = {addr_width{1'bx}};
	
   output [15:0] QA;
   input CLKA;
   input CENA;
   input WENA;
   input [10:0] AA;
   input [15:0] DA;
   input OENA;
   output [15:0] QB;
   input CLKB;
   input CENB;
   input WENB;
   input [10:0] AB;
   input [15:0] DB;
   input OENB;
   wire[15:0] QB_0,QB_1;
    wire msb_of_read_addres =  AB[10];
    wire msb_of_write_addres =  AA[10];

    wire CEN_write_0 = (!OENA) & (CENA | WENA) | (msb_of_write_addres);
    wire CEN_read_0 = OENB | CENB | (!WENB) | (msb_of_read_addres);

    wire CEN_write_1 = (!OENA) & (CENA | WENA) | (!msb_of_write_addres);
    wire CEN_read_1 = OENB | CENB | (!WENB) | (!msb_of_read_addres);

  	drf1024x16 memory_body_0(	.QA(QB_0), .AA(AB[9:0]), .CLKA(CLKB), .CENA(CEN_read_0),
                                      .AB(AA[9:0]), .DB(DA), .CLKB(CLKA), .CENB(CEN_write_0));
  	drf896x16 memory_body_1( .QA(QB_1), .AA(AB[9:0]), .CLKA(CLKB), .CENA(CEN_read_0),
                                      .AB(AA[9:0]), .DB(DA), .CLKB(CLKA), .CENB(CEN_write_0));

    wire[15:0] QB = msb_of_read_addres? QB_1 : QB_0 ;

endmodule