top_median_filter.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	top_median_filter.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is the top module of the median filter circuit.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module top_median_filter(
   clk,
   rst_n,
   ori_hs,
   ori_vs,
   ori_hde,
   ori_vde,
   ori_data,
   active_pixel,
   edge_tol_y,
   edge_tol_uv,
   filter_sel,
   bypass,
   
   des_de,
   des_data,
   hs,
   vs,
   hde,
   vde
);

// Internal Declarations

input         clk;
input         rst_n;
input         ori_hs;
input         ori_vs;
input         ori_hde;
input         ori_vde;
input  [15:0] ori_data;
input  [11:0] active_pixel;
input  [7:0]  edge_tol_y;
input  [7:0]  edge_tol_uv;
input  [1:0]  filter_sel;
input         bypass;

output        des_de;
output [15:0] des_data;
output        hs;
output        vs;
output        hde;
output        vde;


wire        clk;
wire        rst_n;
wire        ori_hs;
wire        ori_vs;
wire        ori_hde;
wire        ori_vde;
wire [15:0] ori_data;
wire [11:0] active_pixel;
wire [7:0]  edge_tol_y;
wire [7:0]  edge_tol_uv;
wire [1:0]  filter_sel;
wire        bypass;

wire        des_de;
wire [15:0] des_data;
wire        hs;
wire        vs;
wire        hde;
wire        vde;

// Local declarations

// Internal signal declarations

//data_gen
wire [7:0]  mdf_y_a31;
wire [7:0]  mdf_y_a32;
wire [7:0]  mdf_y_a33;
wire [7:0]  mdf_uv_a31;
wire [7:0]  mdf_uv_a32;
wire [7:0]  mdf_uv_a33;
wire        extra_vde;
//wr_ctr
wire        line_switch;
wire        wr_en_1;
wire        wr_en_2;
wire [10:0] wr_addr;
wire [7:0]  wr_data_y;
wire [7:0]  wr_data_uv;
wire        hs_wr;
wire        vs_wr;
wire        hde_wr;
wire        vde_wr;
//rd_ctr
wire [7:0]  rd_data_y1;
wire [7:0]  rd_data_y2;
wire [7:0]  rd_data_uv1;
wire [7:0]  rd_data_uv2;
wire [10:0] rd_addr;
wire [7:0]  mdf_y_a11;
wire [7:0]  mdf_y_a12;
wire [7:0]  mdf_y_a13;
wire [7:0]  mdf_y_a21;
wire [7:0]  mdf_y_a22;
wire [7:0]  mdf_y_a23;
wire [7:0]  mdf_uv_a11;
wire [7:0]  mdf_uv_a12;
wire [7:0]  mdf_uv_a13;
wire [7:0]  mdf_uv_a21;
wire [7:0]  mdf_uv_a22;
wire [7:0]  mdf_uv_a23;
wire        hs_rd;
wire        vs_rd;
wire        hde_rd;
wire        vde_bypass;
wire        vde_rd;
//edge_detect
wire        edge_here;
//mdf_y
wire [7:0]  des_data_y;
wire [7:0]  des_data_uv;
wire        hs_des;
wire        vs_des;
wire        hde_des;
wire        vde_des;

// Instances

data_gen generate_data(
   .clk        (clk),
   .rst_n      (rst_n),
   .ori_hs     (ori_hs),
   .ori_vs     (ori_vs),
   .ori_hde    (ori_hde),
   .ori_vde    (ori_vde),
   .ori_data   (ori_data),
   
   .mdf_y_a31  (mdf_y_a31),
   .mdf_y_a32  (mdf_y_a32),
   .mdf_y_a33  (mdf_y_a33),
   .mdf_uv_a31 (mdf_uv_a31),
   .mdf_uv_a32 (mdf_uv_a32),
   .mdf_uv_a33 (mdf_uv_a33),
   .extra_vde  (extra_vde)
);

wr_ctr_mdf write_control(
   .clk         (clk),
   .rst_n       (rst_n),
   .hs          (ori_hs),
   .vs          (ori_vs),
   .hde         (ori_hde),
   .vde         (ori_vde),
   .extra_vde   (extra_vde),
   .data_in_y   (ori_data[15:8]),
   .data_in_uv  (ori_data[7:0]),
   
   .line_switch (line_switch),
   .wr_en_1     (wr_en_1),
   .wr_en_2     (wr_en_2),
   .wr_addr     (wr_addr),
   .wr_data_y   (wr_data_y),
   .wr_data_uv  (wr_data_uv),
   .hs_out      (hs_wr),
   .vs_out      (vs_wr),
   .hde_out     (hde_wr),
   .vde_out     (vde_wr)
);

line_buffers_mdf pixel_ram(
   .clk             (clk),
   .rst_n           (rst_n),
   .wr_en_1         (wr_en_1),
   .wr_en_2         (wr_en_2),
   .wr_addr         (wr_addr),
   .wr_data_y       (wr_data_y),
   .wr_data_uv      (wr_data_uv),
   .rd_addr         (rd_addr),
   
   .rd_data_y1_reg  (rd_data_y1),
   .rd_data_y2_reg  (rd_data_y2),
   .rd_data_uv1_reg (rd_data_uv1),
   .rd_data_uv2_reg (rd_data_uv2)
);
   
rd_ctr_mdf read_control(
   .clk          (clk),
   .rst_n        (rst_n),
   .hs           (ori_hs),
   .vs           (ori_vs),
   .hde          (ori_hde),
   .vde          (ori_vde),
   .extra_vde    (extra_vde),
   .active_pixel (active_pixel),
   .line_switch  (line_switch),
   .rd_data_y1   (rd_data_y1),
   .rd_data_y2   (rd_data_y2),
   .rd_data_uv1  (rd_data_uv1),
   .rd_data_uv2  (rd_data_uv2),
   
   .rd_addr      (rd_addr),
   .mdf_y_a11    (mdf_y_a11),
   .mdf_y_a12    (mdf_y_a12),
   .mdf_y_a13    (mdf_y_a13),
   .mdf_y_a21    (mdf_y_a21),
   .mdf_y_a22    (mdf_y_a22),
   .mdf_y_a23    (mdf_y_a23),
   .mdf_uv_a11   (mdf_uv_a11),
   .mdf_uv_a12   (mdf_uv_a12),
   .mdf_uv_a13   (mdf_uv_a13),
   .mdf_uv_a21   (mdf_uv_a21),
   .mdf_uv_a22   (mdf_uv_a22),
   .mdf_uv_a23   (mdf_uv_a23),
   .hs_out       (hs_rd),
   .vs_out       (vs_rd),
   .hde_out      (hde_rd),
   .vde_1_out    (vde_bypass),
   .vde_2_out    (vde_rd)
);

edge_detect edge_detector(
   .clk         (clk),
   .rst_n       (rst_n),
   .edge_tol_y  (edge_tol_y),
   .edge_tol_uv (edge_tol_uv),
   .mdf_a11     ({mdf_y_a11,mdf_uv_a11}),
   .mdf_a12     ({mdf_y_a12,mdf_uv_a12}),
   .mdf_a13     ({mdf_y_a13,mdf_uv_a13}),
   .mdf_a21     ({mdf_y_a21,mdf_uv_a21}),
   .mdf_a22     ({mdf_y_a22,mdf_uv_a22}),
   .mdf_a23     ({mdf_y_a23,mdf_uv_a23}),
   .mdf_a31     ({mdf_y_a31,mdf_uv_a31}),
   .mdf_a32     ({mdf_y_a32,mdf_uv_a32}),
   .mdf_a33     ({mdf_y_a33,mdf_uv_a33}),
   
   .edge_here   (edge_here)
);

median_filter median_filter(
   .clk         (clk),
   .rst_n       (rst_n),
   .hs          (hs_rd),
   .vs          (vs_rd),
   .hde         (hde_rd),
   .vde         (vde_rd),
   .edge_here   (edge_here),
   .filter_sel  (filter_sel),
   .mdf_a11     ({mdf_y_a11,mdf_uv_a11}),
   .mdf_a12     ({mdf_y_a12,mdf_uv_a12}),
   .mdf_a13     ({mdf_y_a13,mdf_uv_a13}),
   .mdf_a21     ({mdf_y_a21,mdf_uv_a21}),
   .mdf_a22     ({mdf_y_a22,mdf_uv_a22}),
   .mdf_a23     ({mdf_y_a23,mdf_uv_a23}),
   .mdf_a31     ({mdf_y_a31,mdf_uv_a31}),
   .mdf_a32     ({mdf_y_a32,mdf_uv_a32}),
   .mdf_a33     ({mdf_y_a33,mdf_uv_a33}),
   
   .des_data_y  (des_data_y),
   .des_data_uv (des_data_uv),
   .hs_out      (hs_des),
   .vs_out      (vs_des),
   .hde_out     (hde_des),
   .vde_out     (vde_des)
);

yuv_data_out YUV_data_out_reg(
   .clk         (clk),
   .rst_n       (rst_n),
   .hs          (hs_des),
   .vs          (vs_des),
   .hde         (hde_des),
   .vde         (vde_des),
   .vde_bypass  (vde_bypass),
   .des_data_y  (des_data_y),
   .des_data_uv (des_data_uv),
   .bypass      (bypass),
   .ori_data    (ori_data),
   
   .des_de      (des_de),
   .des_data    (des_data),
   .hs_out      (hs),
   .vs_out      (vs),
   .hde_out     (hde),
   .vde_out     (vde)
);

endmodule // top_scaler