edge_detect.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	edge_detect.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the median filter circuit. This file
//            generates the edge detector.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module edge_detect(
   clk,
   rst_n,
   edge_tol_y,
   edge_tol_uv,
   mdf_a11,
   mdf_a12,
   mdf_a13,
   mdf_a21,
   mdf_a22,
   mdf_a23,
   mdf_a31,
   mdf_a32,
   mdf_a33,
   
   edge_here
);


// Internal Declarations

input         clk;
input         rst_n;
input  [7:0]  edge_tol_y;
input  [7:0]  edge_tol_uv;
input  [15:0] mdf_a11;
input  [15:0] mdf_a12;
input  [15:0] mdf_a13;
input  [15:0] mdf_a21;
input  [15:0] mdf_a22;
input  [15:0] mdf_a23;
input  [15:0] mdf_a31;
input  [15:0] mdf_a32;
input  [15:0] mdf_a33;

output        edge_here;


wire        clk;
wire        rst_n;
wire [7:0]  edge_tol_y;
wire [7:0]  edge_tol_uv;
wire [15:0] mdf_a11;
wire [15:0] mdf_a12;
wire [15:0] mdf_a13;
wire [15:0] mdf_a21;
wire [15:0] mdf_a22;
wire [15:0] mdf_a23;
wire [15:0] mdf_a31;
wire [15:0] mdf_a32;
wire [15:0] mdf_a33;

reg         edge_here;

// ### Please start your Verilog code here ###

reg  [7:0]  diff_1_y, diff_2_y, diff_3_y, diff_4_y;
reg  [7:0]  diff_5_y, diff_6_y, diff_7_y, diff_8_y;
reg  [7:0]  diff_1_uv, diff_2_uv, diff_3_uv, diff_4_uv;
reg  [7:0]  diff_5_uv, diff_6_uv, diff_7_uv, diff_8_uv;
reg         edge_y;
reg         edge_uv;
wire        edge_here_tmp;
reg         edge_here_d1, edge_here_d2, edge_here_d3; 

//this always block initializes diff_*_y and generates
//correct diff_*_y
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	diff_1_y<=8'b0;
      	diff_2_y<=8'b0;
      	diff_3_y<=8'b0;
      	diff_4_y<=8'b0;
      	diff_5_y<=8'b0;
      	diff_6_y<=8'b0;
      	diff_7_y<=8'b0;
      	diff_8_y<=8'b0;
	    end
	  else
	    begin
	    	diff_1_y<=(mdf_a22[15:8]>=mdf_a11[15:8])?(mdf_a22[15:8]-mdf_a11[15:8]):(mdf_a11[15:8]-mdf_a22[15:8]);
	    	diff_2_y<=(mdf_a22[15:8]>=mdf_a12[15:8])?(mdf_a22[15:8]-mdf_a12[15:8]):(mdf_a12[15:8]-mdf_a22[15:8]);
	    	diff_3_y<=(mdf_a22[15:8]>=mdf_a13[15:8])?(mdf_a22[15:8]-mdf_a13[15:8]):(mdf_a13[15:8]-mdf_a22[15:8]);
	    	diff_4_y<=(mdf_a22[15:8]>=mdf_a21[15:8])?(mdf_a22[15:8]-mdf_a21[15:8]):(mdf_a21[15:8]-mdf_a22[15:8]);
	    	diff_5_y<=(mdf_a22[15:8]>=mdf_a23[15:8])?(mdf_a22[15:8]-mdf_a23[15:8]):(mdf_a23[15:8]-mdf_a22[15:8]);
	    	diff_6_y<=(mdf_a22[15:8]>=mdf_a31[15:8])?(mdf_a22[15:8]-mdf_a31[15:8]):(mdf_a31[15:8]-mdf_a22[15:8]);
	    	diff_7_y<=(mdf_a22[15:8]>=mdf_a32[15:8])?(mdf_a22[15:8]-mdf_a32[15:8]):(mdf_a32[15:8]-mdf_a22[15:8]);
	    	diff_8_y<=(mdf_a22[15:8]>=mdf_a33[15:8])?(mdf_a22[15:8]-mdf_a33[15:8]):(mdf_a33[15:8]-mdf_a22[15:8]);
      end//else if !rst_n
  end//always

//this always block initializes diff_*_uv and generates
//correct diff_*_uv
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	diff_1_uv<=8'b0;
      	diff_2_uv<=8'b0;
      	diff_3_uv<=8'b0;
      	diff_4_uv<=8'b0;
      	diff_5_uv<=8'b0;
      	diff_6_uv<=8'b0;
      	diff_7_uv<=8'b0;
      	diff_8_uv<=8'b0;
	    end
	  else
	    begin
	    	diff_1_uv<=(mdf_a22[7:0]>=mdf_a11[7:0])?(mdf_a22[7:0]-mdf_a11[7:0]):(mdf_a11[7:0]-mdf_a22[7:0]);
	    	diff_2_uv<=(mdf_a22[7:0]>=mdf_a12[7:0])?(mdf_a22[7:0]-mdf_a12[7:0]):(mdf_a12[7:0]-mdf_a22[7:0]);
	    	diff_3_uv<=(mdf_a22[7:0]>=mdf_a13[7:0])?(mdf_a22[7:0]-mdf_a13[7:0]):(mdf_a13[7:0]-mdf_a22[7:0]);
	    	diff_4_uv<=(mdf_a22[7:0]>=mdf_a21[7:0])?(mdf_a22[7:0]-mdf_a21[7:0]):(mdf_a21[7:0]-mdf_a22[7:0]);
	    	diff_5_uv<=(mdf_a22[7:0]>=mdf_a23[7:0])?(mdf_a22[7:0]-mdf_a23[7:0]):(mdf_a23[7:0]-mdf_a22[7:0]);
	    	diff_6_uv<=(mdf_a22[7:0]>=mdf_a31[7:0])?(mdf_a22[7:0]-mdf_a31[7:0]):(mdf_a31[7:0]-mdf_a22[7:0]);
	    	diff_7_uv<=(mdf_a22[7:0]>=mdf_a32[7:0])?(mdf_a22[7:0]-mdf_a32[7:0]):(mdf_a32[7:0]-mdf_a22[7:0]);
	    	diff_8_uv<=(mdf_a22[7:0]>=mdf_a33[7:0])?(mdf_a22[7:0]-mdf_a33[7:0]):(mdf_a33[7:0]-mdf_a22[7:0]);
      end//else if !rst_n
  end//always
 
assign edge_here_tmp=edge_y&&edge_uv;

//this always block initializes edge_here_d*, edge_here and generates
//correct edge_here_d*, edge_here
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	edge_here_d1<=1'b0;
      	edge_here_d2<=1'b0;
      	edge_here_d3<=1'b0;
      	edge_here<=1'b0;
	    end
	  else
	    begin
	    	edge_here_d1<=edge_here_tmp;
	    	edge_here_d2<=edge_here_d1;
	    	edge_here_d3<=edge_here_d2;
	    	edge_here<=edge_here_d3;
      end//else if !rst_n
  end//always
  
//this always block initializes edge_y, edge_uv and generates
//correct edge_y, edge_uv
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	edge_y<=1'b0;
      	edge_uv<=1'b0;
	    end
	  else
	    begin
	    	if((diff_1_y<=edge_tol_y)||(diff_2_y<=edge_tol_y)||(diff_3_y<=edge_tol_y)||(diff_4_y<=edge_tol_y)
	    	  ||(diff_5_y<=edge_tol_y)||(diff_6_y<=edge_tol_y)||(diff_7_y<=edge_tol_y)||(diff_8_y<=edge_tol_y))
	    	  edge_y<=1'b1;
	    	else
	    	  edge_y<=1'b0;
	    	if((diff_1_uv<=edge_tol_uv)||(diff_2_uv<=edge_tol_uv)||(diff_3_uv<=edge_tol_uv)||(diff_4_uv<=edge_tol_uv)
	    	  ||(diff_5_uv<=edge_tol_uv)||(diff_6_uv<=edge_tol_uv)||(diff_7_uv<=edge_tol_uv)||(diff_8_uv<=edge_tol_uv))
	    	  edge_uv<=1'b1;
	    	else
	    	  edge_uv<=1'b0;
      end//else if !rst_n
  end//always
  
endmodule