data_gen.v

3x3中值滤波 verilog

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME      :	data_gen.v
// TYPE           : parameter
// DEPARTMENT     :	pudn ASIC
// AUTHOR         : Liu Yuxuan, Ye Jian, Liu Lizhuang
// AUTHOR' EMAIL  : [e-mail]
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0  12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :   
//            This module is part of the median filter circuit. This file
//            generates the third line's video data before entering the 3*3
//            matrix median filter of both the Y channel and the UV channel.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains : 
// Critical Timing :
// Test Features :
// Asynchronous I/F : 
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------

`resetall
`timescale 1ns/1ps
module data_gen(
   clk,
   rst_n,
   ori_hs,
   ori_vs,
   ori_hde,
   ori_vde,
   ori_data,
   
   mdf_y_a31,
   mdf_y_a32,
   mdf_y_a33,
   mdf_uv_a31,
   mdf_uv_a32,
   mdf_uv_a33,
   extra_vde
);


// Internal Declarations

input         clk;
input         rst_n;
input         ori_hs;
input         ori_vs;
input         ori_hde;
input         ori_vde;
input  [15:0] ori_data;

output [7:0]  mdf_y_a31;
output [7:0]  mdf_y_a32;
output [7:0]  mdf_y_a33;
output [7:0]  mdf_uv_a31;
output [7:0]  mdf_uv_a32;
output [7:0]  mdf_uv_a33;
output        extra_vde;


wire        clk;
wire        rst_n;
wire        ori_hs;
wire        ori_vs;
wire        ori_hde;
wire        ori_vde;
wire [15:0] ori_data;

reg  [7:0]  mdf_y_a31;
reg  [7:0]  mdf_y_a32;
reg  [7:0]  mdf_y_a33;
reg  [7:0]  mdf_uv_a31;
reg  [7:0]  mdf_uv_a32;
reg  [7:0]  mdf_uv_a33;
reg         extra_vde;

// ### Please start your Verilog code here ###

reg  [15:0] ori_data_d1;
reg  [15:0] ori_data_d2;
reg  [15:0] ori_data_d3;
reg  [15:0] ori_data_d4;
reg         ori_hs_d1;
reg         hs_pulse;
reg         rd_last_line;
//indicate the last line

reg         ori_hde_d1;
reg         ori_hde_d2;
reg         ori_hde_d3;
reg         ori_hde_d4;
reg  [7:0]  mdf_y_a31_a2, mdf_y_a31_a1;
reg  [7:0]  mdf_y_a32_a2, mdf_y_a32_a1;
reg  [7:0]  mdf_y_a33_a2, mdf_y_a33_a1;
reg  [7:0]  mdf_uv_a31_a2, mdf_uv_a31_a1;
reg  [7:0]  mdf_uv_a32_a2, mdf_uv_a32_a1;
reg  [7:0]  mdf_uv_a33_a2, mdf_uv_a33_a1;

//this always block generates ori_data registers
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        ori_data_d1<=16'b0;
        ori_data_d2<=16'b0;
        ori_data_d3<=16'b0;
        ori_data_d4<=16'b0;
	    end
	  else
	    begin
        ori_data_d1<=ori_data;
        ori_data_d2<=ori_data_d1;
        ori_data_d3<=ori_data_d2;
        ori_data_d4<=ori_data_d3;
      end//else if !rst_n
  end//always

//this always block generates 3x3 median filter values
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
        mdf_y_a31_a1<=8'b0;
        mdf_y_a32_a1<=8'b0;
        mdf_y_a33_a1<=8'b0;
        mdf_y_a31<=8'b0;
        mdf_y_a32<=8'b0;
        mdf_y_a33<=8'b0;
        mdf_uv_a31_a1<=8'b0;
        mdf_uv_a32_a1<=8'b0;
        mdf_uv_a33_a1<=8'b0;
        mdf_uv_a31<=8'b0;
        mdf_uv_a32<=8'b0;
        mdf_uv_a33<=8'b0;
	    end
	  else
	    begin
        mdf_y_a31_a1<=mdf_y_a31_a2;
        mdf_y_a32_a1<=mdf_y_a32_a2;
        mdf_y_a33_a1<=mdf_y_a33_a2;
        mdf_y_a31<=mdf_y_a31_a1;
        mdf_y_a32<=mdf_y_a32_a1;
        mdf_y_a33<=mdf_y_a33_a1;
        mdf_uv_a31_a1<=mdf_uv_a31_a2;
        mdf_uv_a32_a1<=mdf_uv_a32_a2;
        mdf_uv_a33_a1<=mdf_uv_a33_a2;
        mdf_uv_a31<=mdf_uv_a31_a1;
        mdf_uv_a32<=mdf_uv_a32_a1;
        mdf_uv_a33<=mdf_uv_a33_a1;
      end//else if !rst_n
  end//always

//this always block generates hs_pulse
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      hs_pulse<=1'b0;
	  else
	    begin
        if(ori_hs && (!ori_hs_d1))
          hs_pulse<=1'b1;
        else
          hs_pulse<=1'b0;
      end//else if !rst_n
  end//always
  
//this always block initializes rd_last_line and generates
//correct rd_last_line
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	extra_vde<=1'b0;
        rd_last_line<=1'b0;
	    end
	  else
	    begin
	    	if(ori_vs)
	    	  extra_vde<=1'b0;
        if(ori_vde)
          extra_vde<=1'b1;
        if(extra_vde && (!ori_vde) && hs_pulse)
          rd_last_line<=1'b1;
        if(rd_last_line && hs_pulse)
          begin
          	extra_vde<=1'b0;
            rd_last_line<=1'b0;
          end
      end//else if !rst_n
  end//always
  
//this always block initializes mdf_y_a*, mdf_uv_a* and generates
//correct mdf_y_a*, mdf_uv_a* for median filter
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	mdf_y_a31_a2<=8'b0;
      	mdf_y_a32_a2<=8'b0;
      	mdf_y_a33_a2<=8'b0;
      	mdf_uv_a31_a2<=8'b0;
      	mdf_uv_a32_a2<=8'b0;
      	mdf_uv_a33_a2<=8'b0;
	    end
	  else
	    begin
	    	if(extra_vde)
	    	  begin
            if(ori_hde_d2&&(!ori_hde_d3))//for first column
              begin
            	  mdf_y_a31_a2<=ori_data_d2[15:8];
                mdf_y_a32_a2<=ori_data_d2[15:8];
                mdf_y_a33_a2<=ori_data_d1[15:8];
                mdf_uv_a31_a2<=ori_data_d2[7:0];
                mdf_uv_a32_a2<=ori_data_d2[7:0];
                mdf_uv_a33_a2<=ori_data[7:0];
              end
            else if(ori_hde_d3&&(!ori_hde_d4))//for second column
              begin
            	  mdf_y_a31_a2<=ori_data_d3[15:8];
                mdf_y_a32_a2<=ori_data_d2[15:8];
                mdf_y_a33_a2<=ori_data_d1[15:8];
                mdf_uv_a31_a2<=ori_data_d3[7:0];
                mdf_uv_a32_a2<=ori_data_d3[7:0];
                mdf_uv_a33_a2<=ori_data_d1[7:0];
              end
            else if((!ori_hde_d1)&&ori_hde_d2)//for last column
              begin
               	mdf_y_a31_a2<=ori_data_d2[7:0];
                mdf_y_a32_a2<=ori_data_d1[7:0];
                mdf_y_a33_a2<=ori_data_d1[7:0];
                mdf_uv_a31_a2<=ori_data_d2[7:0];
                mdf_uv_a32_a2<=ori_data[7:0];
                mdf_uv_a33_a2<=ori_data[7:0];
              end
            else if((!ori_hde_d1)&&ori_hde_d2)//for last 2 column
              begin
               	mdf_y_a31_a2<=ori_data_d3[7:0];
                mdf_y_a32_a2<=ori_data_d2[7:0];
                mdf_y_a33_a2<=ori_data_d1[7:0];
                mdf_uv_a31_a2<=ori_data_d3[7:0];
                mdf_uv_a32_a2<=ori_data_d1[7:0];
                mdf_uv_a33_a2<=ori_data_d1[7:0];
              end
            else if(ori_hde_d4)
	    	      begin
                mdf_y_a31_a2<=ori_data_d3[15:8];
                mdf_y_a32_a2<=ori_data_d2[15:8];
                mdf_y_a33_a2<=ori_data_d1[15:8];
                mdf_uv_a31_a2<=ori_data_d4[7:0];
                mdf_uv_a32_a2<=ori_data_d2[7:0];
                mdf_uv_a33_a2<=ori_data[7:0];
              end
          end//if ori_vde
        else//need to add special treatment for last line
          begin
          	mdf_y_a31_a2<=8'b0;
            mdf_y_a32_a2<=8'b0;
            mdf_y_a33_a2<=8'b0;
            mdf_uv_a31_a2<=8'b0;
            mdf_uv_a32_a2<=8'b0;
            mdf_uv_a33_a2<=8'b0;
          end
      end//else if !rst_n
  end//always

//this always block initializes ori_hs_d1 and generates
//correct ori_hs_d1
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      ori_hs_d1<=1'b0;
	  else
	    ori_hs_d1<=ori_hs;
  end//always
  
//this always block initializes ori_hde_d* and generates
//correct ori_hde_d*
always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
      begin
      	ori_hde_d1<=1'b0;
      	ori_hde_d2<=1'b0;
      	ori_hde_d3<=1'b0;
      	ori_hde_d4<=1'b0;
	    end
	  else
	    begin
	    	ori_hde_d1<=ori_hde;
        ori_hde_d2<=ori_hde_d1;
        ori_hde_d3<=ori_hde_d2;
        ori_hde_d4<=ori_hde_d3;
      end//else if !rst_n
  end//always

endmodule