send_timesim.vhd

自己在ISE下用VHDL写的UART

      SRST => count_6_SRINV,
      O => count(6)
    );
  databuffer_7_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_7_DELCHAIN_DELCH_OUT,
      O => databuffer_7_I1
    );
  databuffer_7_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_7_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_7_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_7_DLYCE,
      GSR => GSR,
      I => databuffer_7_DELCHAIN_IDELAYMUX,
      INC => databuffer_7_DLYINC,
      RST => databuffer_7_DLYRST
    );
  databuffer_7_DELCHAIN_IDELAYMUX_116 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_7_IBUF,
      O => databuffer_7_DELCHAIN_IDELAYMUX
    );
  databuffer_6_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_6_IFF_IFF1,
      O => databuffer(6)
    );
  databuffer_6_IFF_CLKINV_117 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_6_IFF_CLKINV
    );
  databuffer_6_IFF_CE1INV_118 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_6_IFF_CE1INV
    );
  databuffer_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_6_I1,
      CE => databuffer_6_IFF_CE1INV,
      CLK => databuffer_6_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_6_IFF_IFF1
    );
  busy_OBUF_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => busy_OBUF_OFF_OFF1,
      O => busy_OBUF
    );
  busy_OBUF_OFF_OSRUSED_119 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => busy_OBUF_OFF_OSRUSED
    );
  busy_OBUF_OFF_D1INV_120 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => busy_OBUF_OFF_D1INV
    );
  databuffer_7_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_7_IFF_IFF1,
      O => databuffer(7)
    );
  databuffer_7_IFF_CLKINV_121 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_7_IFF_CLKINV
    );
  databuffer_7_IFF_CE1INV_122 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_7_IFF_CE1INV
    );
  databuffer_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_7_I1,
      CE => databuffer_7_IFF_CE1INV,
      CLK => databuffer_7_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_7_IFF_IFF1
    );
  busy_123 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => busy_OBUF_OFF_D1INV,
      CE => VCC,
      CLK => busy_OBUF_C1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => busy_OBUF_OFF_OSRUSED,
      O => busy_OBUF_OFF_OFF1
    );
  t_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => t_OFF_OFF1,
      O => t
    );
  t_OFF_OCEINV_124 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => t_OFF_OCEINV
    );
  t_OFF_D1INV_125 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001739_O,
      O => t_OFF_D1INV
    );
  t_126 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => t_OFF_D1INV,
      CE => t_OFF_OCEINV,
      CLK => t_C1INV,
      SET => t_OFF_OFF1_SET,
      RST => GND,
      O => t_OFF_OFF1
    );
  t_OFF_OFF1_SETOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => t_OFF_OFF1_SET
    );
  databuffer_3_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_3_DELCHAIN_DELCH_OUT,
      O => databuffer_3_I1
    );
  databuffer_3_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_3_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_3_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_3_DLYCE,
      GSR => GSR,
      I => databuffer_3_DELCHAIN_IDELAYMUX,
      INC => databuffer_3_DLYINC,
      RST => databuffer_3_DLYRST
    );
  databuffer_3_DELCHAIN_IDELAYMUX_127 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_3_IBUF,
      O => databuffer_3_DELCHAIN_IDELAYMUX
    );
  databuffer_2_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_2_IFF_IFF1,
      O => databuffer(2)
    );
  databuffer_2_IFF_CLKINV_128 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_2_IFF_CLKINV
    );
  databuffer_2_IFF_CE1INV_129 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_2_IFF_CE1INV
    );
  databuffer_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_2_I1,
      CE => databuffer_2_IFF_CE1INV,
      CLK => databuffer_2_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_2_IFF_IFF1
    );
  databuffer_4_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_4_DELCHAIN_DELCH_OUT,
      O => databuffer_4_I1
    );
  databuffer_4_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_4_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_4_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_4_DLYCE,
      GSR => GSR,
      I => databuffer_4_DELCHAIN_IDELAYMUX,
      INC => databuffer_4_DLYINC,
      RST => databuffer_4_DLYRST
    );
  databuffer_4_DELCHAIN_IDELAYMUX_130 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_4_IBUF,
      O => databuffer_4_DELCHAIN_IDELAYMUX
    );
  databuffer_3_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_3_IFF_IFF1,
      O => databuffer(3)
    );
  databuffer_3_IFF_CLKINV_131 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_3_IFF_CLKINV
    );
  databuffer_3_IFF_CE1INV_132 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_3_IFF_CE1INV
    );
  databuffer_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_3_I1,
      CE => databuffer_3_IFF_CE1INV,
      CLK => databuffer_3_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_3_IFF_IFF1
    );
  databuffer_5_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_5_DELCHAIN_DELCH_OUT,
      O => databuffer_5_I1
    );
  databuffer_5_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_5_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_5_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_5_DLYCE,
      GSR => GSR,
      I => databuffer_5_DELCHAIN_IDELAYMUX,
      INC => databuffer_5_DLYINC,
      RST => databuffer_5_DLYRST
    );
  databuffer_5_DELCHAIN_IDELAYMUX_133 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_5_IBUF,
      O => databuffer_5_DELCHAIN_IDELAYMUX
    );
  databuffer_4_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_4_IFF_IFF1,
      O => databuffer(4)
    );
  databuffer_4_IFF_CLKINV_134 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_4_IFF_CLKINV
    );
  databuffer_4_IFF_CE1INV_135 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_4_IFF_CE1INV
    );
  databuffer_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_4_I1,
      CE => databuffer_4_IFF_CE1INV,
      CLK => databuffer_4_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_4_IFF_IFF1
    );
  databuffer_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_5_I1,
      CE => databuffer_5_IFF_CE1INV,
      CLK => databuffer_5_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_5_IFF_IFF1
    );
  databuffer_5_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_5_IFF_IFF1,
      O => databuffer(5)
    );
  databuffer_5_IFF_CLKINV_136 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_5_IFF_CLKINV
    );
  databuffer_5_IFF_CE1INV_137 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_5_IFF_CE1INV
    );
  databuffer_6_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_6_DELCHAIN_DELCH_OUT,
      O => databuffer_6_I1
    );
  databuffer_6_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_6_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_6_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_6_DLYCE,
      GSR => GSR,
      I => databuffer_6_DELCHAIN_IDELAYMUX,
      INC => databuffer_6_DLYINC,
      RST => databuffer_6_DLYRST
    );
  databuffer_6_DELCHAIN_IDELAYMUX_138 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_6_IBUF,
      O => databuffer_6_DELCHAIN_IDELAYMUX
    );
  Q_n001432 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => count(6),
      ADR1 => count(7),
      ADR2 => Q_n00148_O,
      ADR3 => CHOICE39,
      O => Q_n0014_F
    );
  Q_n001811 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd7,
      ADR1 => c_FFd6,
      ADR2 => CHOICE19,
      ADR3 => c_FFd5,
      O => flag2_G
    );
  Q_n001835 : X_LUT4
    generic map(
      INIT => X"FDA8"
    )
    port map (
      ADR0 => flag2,
      ADR1 => CHOICE18,
      ADR2 => Q_n001811_O,
      ADR3 => c_FFd1,
      O => Q_n001835_O
    );
  Q_n001722 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => databuffer(6),
      ADR1 => VCC,
      ADR2 => c_FFd3,
      ADR3 => VCC,
      O => CHOICE13_G
    );
  flag2_139 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => flag2_DXMUX,
      CE => flag2_CEINV,
      CLK => flag2_CLKINV,
      SET => GND,
      RST => flag2_FFX_RST,
      O => flag2
    );
  flag2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => flag2_FFX_RST
    );
  Q_n00148 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => count(5),
      ADR1 => count(4),
      ADR2 => count(2),
      ADR3 => count(3),
      O => Q_n0014_G
    );
  Q_n001712 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => c_FFd7,
      ADR1 => CHOICE1,
      ADR2 => CHOICE5,
      ADR3 => databuffer(2),
      O => Q_n001739_O_G
    );
  Q_n001728 : X_LUT4
    generic map(
      INIT => X"FEFA"
    )
    port map (
      ADR0 => c_FFd1,
      ADR1 => databuffer(1),
      ADR2 => Q_n001722_O,
      ADR3 => c_FFd8,
      O => CHOICE13_F
    );
  Q_n001739 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => CHOICE13,
      ADR1 => VCC,
      ADR2 => CHOICE9,
      ADR3 => Q_n001712_O,
      O => Q_n001739_O_F
    );
  load_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => load_BUFGP_IBUFG,
      O => load_BUFGP
    );
  clk_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk_BUFGP_IBUFG,
      O => clk_BUFGP
    );
  PWR_VCC_0_LOGICAL_ZERO : X_ZERO
    port map (
      O => PWR_VCC_0_GND
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  PWR_VCC_1_LOGICAL_ZERO : X_ZERO
    port map (
      O => PWR_VCC_1_GND
    );
  PWR_VCC_1_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1_0
    );
  count_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_0_G
    );
  count_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => count(2),
      ADR3 => VCC,
      O => count_2_F
    );
  count_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => count(3),
      O => count_2_G
    );
  count_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => count(4),
      ADR3 => VCC,
      O => count_4_F
    );
  count_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => count(5),
      O => count_4_G
    );
  count_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_6_F
    );
  count_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => count(7),
      O => count_6_G
    );
  count_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => count(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_8_F
    );
  NlwBlock_send_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_send_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;