send_timesim.vhd

自己在ISE下用VHDL写的UART

    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_INBUF_B,
      O => load_BUFGP_IBUFG
    );
  load_BUFGP_IBUFG_93 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load,
      O => load_INBUF_B
    );
  load_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => load_ENABLE
    );
  busy_OBUF_CLK1INV : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => busy_OBUF_C1INV
    );
  t_CLK1INV : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => t_C1INV
    );
  c_FFd1_94 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd2_DYMUX,
      CE => c_FFd2_CEINV,
      CLK => c_FFd2_CLKINV,
      SET => GND,
      RST => c_FFd2_FFY_RST,
      O => c_FFd1
    );
  c_FFd2_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd2_FFY_RST
    );
  flag2_DXMUX_95 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001835_O,
      O => flag2_DXMUX
    );
  flag2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag2_G,
      O => Q_n001811_O
    );
  flag2_CLKINV_96 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => flag2_CLKINV
    );
  flag2_CEINV_97 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => flag2_CEINV
    );
  Q_n0014_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014_F,
      O => Q_n0014
    );
  Q_n0014_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014_G,
      O => Q_n00148_O
    );
  CHOICE13_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE13_F,
      O => CHOICE13
    );
  CHOICE13_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE13_G,
      O => Q_n001722_O
    );
  Q_n001739_O_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001739_O_F,
      O => Q_n001739_O
    );
  Q_n001739_O_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001739_O_G,
      O => Q_n001712_O
    );
  c_FFd2_98 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd2_DXMUX,
      CE => c_FFd2_CEINV,
      CLK => c_FFd2_CLKINV,
      SET => GND,
      RST => c_FFd2_FFX_RST,
      O => c_FFd2
    );
  c_FFd2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd2_FFX_RST
    );
  c_FFd3_99 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd4_DYMUX,
      CE => c_FFd4_CEINV,
      CLK => c_FFd4_CLKINV,
      SET => GND,
      RST => c_FFd4_FFY_RST,
      O => c_FFd3
    );
  c_FFd4_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd4_FFY_RST
    );
  c_FFd4_100 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd4_DXMUX,
      CE => c_FFd4_CEINV,
      CLK => c_FFd4_CLKINV,
      SET => GND,
      RST => c_FFd4_FFX_RST,
      O => c_FFd4
    );
  c_FFd4_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd4_FFX_RST
    );
  c_FFd5_101 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd6_DYMUX,
      CE => c_FFd6_CEINV,
      CLK => c_FFd6_CLKINV,
      SET => GND,
      RST => c_FFd6_FFY_RST,
      O => c_FFd5
    );
  c_FFd6_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd6_FFY_RST
    );
  c_FFd6_102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd6_DXMUX,
      CE => c_FFd6_CEINV,
      CLK => c_FFd6_CLKINV,
      SET => GND,
      RST => c_FFd6_FFX_RST,
      O => c_FFd6
    );
  c_FFd6_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd6_FFX_RST
    );
  c_FFd7_103 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd8_DYMUX,
      CE => c_FFd8_CEINV,
      CLK => c_FFd8_CLKINV,
      SET => GND,
      RST => c_FFd8_FFY_RST,
      O => c_FFd7
    );
  c_FFd8_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd8_FFY_RST
    );
  c_FFd8_104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd8_DXMUX,
      CE => c_FFd8_CEINV,
      CLK => c_FFd8_CLKINV,
      SET => GND,
      RST => c_FFd8_FFX_RST,
      O => c_FFd8
    );
  c_FFd8_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd8_FFX_RST
    );
  Q_n001422 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => count(8),
      ADR1 => count(9),
      ADR2 => count(1),
      ADR3 => count(0),
      O => CHOICE39_F
    );
  c_FFd9_105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd10_DYMUX,
      CE => c_FFd10_CEINV,
      CLK => c_FFd10_CLKINV,
      SET => GND,
      RST => c_FFd10_FFY_RST,
      O => c_FFd9
    );
  c_FFd10_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd10_FFY_RST
    );
  c_FFd10_106 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => c_FFd10_DXMUX,
      CE => c_FFd10_CEINV,
      CLK => c_FFd10_CLKINV,
      SET => c_FFd10_FFX_SET,
      RST => GND,
      O => c_FFd10
    );
  c_FFd10_FFX_SETOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd10_FFX_SET
    );
  Mxor_flag3_Result1 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => flag1,
      ADR2 => VCC,
      ADR3 => flag2,
      O => flag1_G
    );
  flag1_107 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => flag1_DYMUX,
      CE => flag1_CEINV,
      CLK => flag1_CLKINV,
      SET => GND,
      RST => flag1_FFY_RST,
      O => flag1
    );
  flag1_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => flag1_FFY_RST
    );
  flag1_N691 : X_LUT4
    generic map(
      INIT => X"CC33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => flag1,
      ADR2 => VCC,
      ADR3 => flag2,
      O => flag1_F
    );
  count_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DYMUX,
      CE => VCC,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_0_SRINV,
      O => count(1)
    );
  count_LPM_COUNTER_1_n0000_0_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => count(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_N433
    );
  databuffer_0_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_0_DELCHAIN_DELCH_OUT,
      O => databuffer_0_I1
    );
  DELCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_0_DELCHAIN_DELCH_OUT,
      C => NLW_DELCHAIN_C_UNCONNECTED,
      CE => databuffer_0_DLYCE,
      GSR => GSR,
      I => databuffer_0_DELCHAIN_IDELAYMUX,
      INC => databuffer_0_DLYINC,
      RST => databuffer_0_DLYRST
    );
  databuffer_0_DELCHAIN_IDELAYMUX_108 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_0_IBUF,
      O => databuffer_0_DELCHAIN_IDELAYMUX
    );
  databuffer_1_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_1_DELCHAIN_DELCH_OUT,
      O => databuffer_1_I1
    );
  databuffer_1_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_1_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_1_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_1_DLYCE,
      GSR => GSR,
      I => databuffer_1_DELCHAIN_IDELAYMUX,
      INC => databuffer_1_DLYINC,
      RST => databuffer_1_DLYRST
    );
  databuffer_1_DELCHAIN_IDELAYMUX_109 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_1_IBUF,
      O => databuffer_1_DELCHAIN_IDELAYMUX
    );
  databuffer_0_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_0_IFF_IFF1,
      O => databuffer(0)
    );
  databuffer_0_IFF_CLKINV_110 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_0_IFF_CLKINV
    );
  databuffer_0_IFF_CE1INV_111 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_0_IFF_CE1INV
    );
  databuffer_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_0_I1,
      CE => databuffer_0_IFF_CE1INV,
      CLK => databuffer_0_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_0_IFF_IFF1
    );
  databuffer_2_DELCHAIN_IFFMUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_2_DELCHAIN_DELCH_OUT,
      O => databuffer_2_I1
    );
  databuffer_2_DELCHAIN_DELAYCHAIN : X_IDELAY
    generic map(
      SIM_TAPDELAY_VALUE => 78
    )
    port map (
      O => databuffer_2_DELCHAIN_DELCH_OUT,
      C => NLW_databuffer_2_DELCHAIN_DELAYCHAIN_C_UNCONNECTED,
      CE => databuffer_2_DLYCE,
      GSR => GSR,
      I => databuffer_2_DELCHAIN_IDELAYMUX,
      INC => databuffer_2_DLYINC,
      RST => databuffer_2_DLYRST
    );
  databuffer_2_DELCHAIN_IDELAYMUX_112 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_2_IBUF,
      O => databuffer_2_DELCHAIN_IDELAYMUX
    );
  databuffer_1_IFF_Q1MUX : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => databuffer_1_IFF_IFF1,
      O => databuffer(1)
    );
  databuffer_1_IFF_CLKINV_113 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => databuffer_1_IFF_CLKINV
    );
  databuffer_1_IFF_CE1INV_114 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => databuffer_1_IFF_CE1INV
    );
  databuffer_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => databuffer_1_I1,
      CE => databuffer_1_IFF_CE1INV,
      CLK => databuffer_1_IFF_CLKINV,
      SET => GSR,
      RST => GND,
      O => databuffer_1_IFF_IFF1
    );
  count_9 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_8_DYMUX,
      CE => VCC,
      CLK => count_8_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_8_SRINV,
      O => count(9)
    );
  count_8 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_8_DXMUX,
      CE => VCC,
      CLK => count_8_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_8_SRINV,
      O => count(8)
    );
  count_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DXMUX,
      CE => VCC,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_0_SRINV,
      O => count(0)
    );
  count_3 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_2_DYMUX,
      CE => VCC,
      CLK => count_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_2_SRINV,
      O => count(3)
    );
  count_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_2_DXMUX,
      CE => VCC,
      CLK => count_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_2_SRINV,
      O => count(2)
    );
  count_9_rt_115 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_9_rt
    );
  count_5 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_4_DYMUX,
      CE => VCC,
      CLK => count_4_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_4_SRINV,
      O => count(5)
    );
  count_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_4_DXMUX,
      CE => VCC,
      CLK => count_4_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_4_SRINV,
      O => count(4)
    );
  count_7 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_6_DYMUX,
      CE => VCC,
      CLK => count_6_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_6_SRINV,
      O => count(7)
    );
  count_6 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_6_DXMUX,
      CE => VCC,
      CLK => count_6_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,