send_timesim.vhd

自己在ISE下用VHDL写的UART

      I => count_N433,
      O => count_0_DXMUX
    );
  count_0_CYMUXF : X_MUX2
    port map (
      IA => count_0_LOGIC_ONE,
      IB => count_0_CYINIT,
      SEL => count_N433,
      O => count_LPM_COUNTER_1_n0000_0_cyo
    );
  count_0_CYINIT_29 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_0_BXINVNOT,
      O => count_0_CYINIT
    );
  count_0_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_0,
      O => count_0_BXINVNOT
    );
  count_0_DYMUX_30 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_0_XORG,
      O => count_0_DYMUX
    );
  count_0_XORG_31 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_0_cyo,
      I1 => count_0_G,
      O => count_0_XORG
    );
  count_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_0_CYMUXG,
      O => count_LPM_COUNTER_1_n0000_1_cyo
    );
  count_0_CYMUXG_32 : X_MUX2
    port map (
      IA => count_0_LOGIC_ZERO,
      IB => count_LPM_COUNTER_1_n0000_0_cyo,
      SEL => count_0_G,
      O => count_0_CYMUXG
    );
  count_0_SRINV_33 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => count_0_SRINV
    );
  count_0_CLKINV_34 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_0_CLKINV
    );
  count_2_LOGIC_ZERO_35 : X_ZERO
    port map (
      O => count_2_LOGIC_ZERO
    );
  count_2_DXMUX_36 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_XORF,
      O => count_2_DXMUX
    );
  count_2_XORF_37 : X_XOR2
    port map (
      I0 => count_2_CYINIT,
      I1 => count_2_F,
      O => count_2_XORF
    );
  count_2_CYMUXF : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_CYINIT,
      SEL => count_2_F,
      O => count_LPM_COUNTER_1_n0000_2_cyo
    );
  count_2_CYMUXF2_38 : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_LOGIC_ZERO,
      SEL => count_2_F,
      O => count_2_CYMUXF2
    );
  count_2_CYINIT_39 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_1_cyo,
      O => count_2_CYINIT
    );
  count_2_DYMUX_40 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_XORG,
      O => count_2_DYMUX
    );
  count_2_XORG_41 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_2_cyo,
      I1 => count_2_G,
      O => count_2_XORG
    );
  count_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_3_cyo
    );
  count_2_FASTCARRY_42 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_1_cyo,
      O => count_2_FASTCARRY
    );
  count_2_CYAND_43 : X_AND2
    port map (
      I0 => count_2_G,
      I1 => count_2_F,
      O => count_2_CYAND
    );
  count_2_CYMUXFAST_44 : X_MUX2
    port map (
      IA => count_2_CYMUXG2,
      IB => count_2_FASTCARRY,
      SEL => count_2_CYAND,
      O => count_2_CYMUXFAST
    );
  count_2_CYMUXG2_45 : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_CYMUXF2,
      SEL => count_2_G,
      O => count_2_CYMUXG2
    );
  count_2_SRINV_46 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => count_2_SRINV
    );
  count_2_CLKINV_47 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_2_CLKINV
    );
  count_4_LOGIC_ZERO_48 : X_ZERO
    port map (
      O => count_4_LOGIC_ZERO
    );
  count_4_DXMUX_49 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_XORF,
      O => count_4_DXMUX
    );
  count_4_XORF_50 : X_XOR2
    port map (
      I0 => count_4_CYINIT,
      I1 => count_4_F,
      O => count_4_XORF
    );
  count_4_CYMUXF : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_CYINIT,
      SEL => count_4_F,
      O => count_LPM_COUNTER_1_n0000_4_cyo
    );
  count_4_CYMUXF2_51 : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_LOGIC_ZERO,
      SEL => count_4_F,
      O => count_4_CYMUXF2
    );
  count_4_CYINIT_52 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_3_cyo,
      O => count_4_CYINIT
    );
  count_4_DYMUX_53 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_XORG,
      O => count_4_DYMUX
    );
  count_4_XORG_54 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_4_cyo,
      I1 => count_4_G,
      O => count_4_XORG
    );
  count_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_5_cyo
    );
  count_4_FASTCARRY_55 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_3_cyo,
      O => count_4_FASTCARRY
    );
  count_4_CYAND_56 : X_AND2
    port map (
      I0 => count_4_G,
      I1 => count_4_F,
      O => count_4_CYAND
    );
  count_4_CYMUXFAST_57 : X_MUX2
    port map (
      IA => count_4_CYMUXG2,
      IB => count_4_FASTCARRY,
      SEL => count_4_CYAND,
      O => count_4_CYMUXFAST
    );
  count_4_CYMUXG2_58 : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_CYMUXF2,
      SEL => count_4_G,
      O => count_4_CYMUXG2
    );
  count_4_SRINV_59 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => count_4_SRINV
    );
  count_4_CLKINV_60 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_4_CLKINV
    );
  count_6_LOGIC_ZERO_61 : X_ZERO
    port map (
      O => count_6_LOGIC_ZERO
    );
  count_6_DXMUX_62 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_XORF,
      O => count_6_DXMUX
    );
  count_6_XORF_63 : X_XOR2
    port map (
      I0 => count_6_CYINIT,
      I1 => count_6_F,
      O => count_6_XORF
    );
  count_6_CYMUXF : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_CYINIT,
      SEL => count_6_F,
      O => count_LPM_COUNTER_1_n0000_6_cyo
    );
  count_6_CYMUXF2_64 : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_LOGIC_ZERO,
      SEL => count_6_F,
      O => count_6_CYMUXF2
    );
  count_6_CYINIT_65 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_5_cyo,
      O => count_6_CYINIT
    );
  count_6_DYMUX_66 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_XORG,
      O => count_6_DYMUX
    );
  count_6_XORG_67 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_6_cyo,
      I1 => count_6_G,
      O => count_6_XORG
    );
  count_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_7_cyo
    );
  count_6_FASTCARRY_68 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_5_cyo,
      O => count_6_FASTCARRY
    );
  count_6_CYAND_69 : X_AND2
    port map (
      I0 => count_6_G,
      I1 => count_6_F,
      O => count_6_CYAND
    );
  count_6_CYMUXFAST_70 : X_MUX2
    port map (
      IA => count_6_CYMUXG2,
      IB => count_6_FASTCARRY,
      SEL => count_6_CYAND,
      O => count_6_CYMUXFAST
    );
  count_6_CYMUXG2_71 : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_CYMUXF2,
      SEL => count_6_G,
      O => count_6_CYMUXG2
    );
  count_6_SRINV_72 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => count_6_SRINV
    );
  count_6_CLKINV_73 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_6_CLKINV
    );
  count_8_LOGIC_ZERO_74 : X_ZERO
    port map (
      O => count_8_LOGIC_ZERO
    );
  count_8_DXMUX_75 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_8_XORF,
      O => count_8_DXMUX
    );
  count_8_XORF_76 : X_XOR2
    port map (
      I0 => count_8_CYINIT,
      I1 => count_8_F,
      O => count_8_XORF
    );
  count_8_CYMUXF : X_MUX2
    port map (
      IA => count_8_LOGIC_ZERO,
      IB => count_8_CYINIT,
      SEL => count_8_F,
      O => count_LPM_COUNTER_1_n0000_8_cyo
    );
  count_8_CYINIT_77 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_7_cyo,
      O => count_8_CYINIT
    );
  count_8_DYMUX_78 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_8_XORG,
      O => count_8_DYMUX
    );
  count_8_XORG_79 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_8_cyo,
      I1 => count_9_rt,
      O => count_8_XORG
    );
  count_8_SRINV_80 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => count_8_SRINV
    );
  count_8_CLKINV_81 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_8_CLKINV
    );
  data_0_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_0_INBUF_B,
      O => data_0_IBUF
    );
  data_0_IBUF_82 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(0),
      O => data_0_INBUF_B
    );
  data_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_0_ENABLE
    );
  data_1_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_1_INBUF_B,
      O => data_1_IBUF
    );
  data_1_IBUF_83 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(1),
      O => data_1_INBUF_B
    );
  data_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_1_ENABLE
    );
  clk_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_INBUF_B,
      O => clk_BUFGP_IBUFG
    );
  clk_BUFGP_IBUFG_84 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk,
      O => clk_INBUF_B
    );
  clk_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => clk_ENABLE
    );
  data_2_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_2_INBUF_B,
      O => data_2_IBUF
    );
  data_2_IBUF_85 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(2),
      O => data_2_INBUF_B
    );
  data_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_2_ENABLE
    );
  data_3_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_3_INBUF_B,
      O => data_3_IBUF
    );
  data_3_IBUF_86 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(3),
      O => data_3_INBUF_B
    );
  data_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_3_ENABLE
    );
  data_4_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_4_INBUF_B,
      O => data_4_IBUF
    );
  data_4_IBUF_87 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(4),
      O => data_4_INBUF_B
    );
  data_4_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_4_ENABLE
    );
  data_5_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_5_INBUF_B,
      O => data_5_IBUF
    );
  data_5_IBUF_88 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(5),
      O => data_5_INBUF_B
    );
  data_5_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_5_ENABLE
    );
  data_6_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_6_INBUF_B,
      O => data_6_IBUF
    );
  data_6_IBUF_89 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(6),
      O => data_6_INBUF_B
    );
  data_6_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_6_ENABLE
    );
  clkdiv_90 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => clkdiv_DYMUX,
      CE => clkdiv_CEINV,
      CLK => clkdiv_CLKINV,
      SET => GND,
      RST => clkdiv_FFY_RST,
      O => clkdiv
    );
  clkdiv_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => clkdiv_FFY_RST
    );
  data_7_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_7_INBUF_B,
      O => data_7_IBUF
    );
  data_7_IBUF_91 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data(7),
      O => data_7_INBUF_B
    );
  data_7_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_7_ENABLE
    );
  busy_OBUF_92 : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => busy_OBUF,
      CTL => busy_ENABLE,
      O => busy
    );
  busy_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => busy_ENABLE
    );
  TXD_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => t,
      CTL => TXD_ENABLE,
      O => TXD
    );
  TXD_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => TXD_ENABLE
    );
  load_INBUF_USED : X_BUF_PP