send_timesim.vhd

自己在ISE下用VHDL写的UART

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 10 -pcf send.pcf -ngm send.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim send.ncd send_timesim.vhd 
-- Input file    : send.ncd
-- Output file   : send_timesim.vhd
-- Design name   : send
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 4vlx25sf363-10 (PREVIEW 1.46 2004-07-09)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity send is
  port (
    TXD : out STD_LOGIC; 
    busy : out STD_LOGIC; 
    load : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    data : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end send;

architecture Structure of send is
  signal c_FFd2 : STD_LOGIC; 
  signal c_FFd4 : STD_LOGIC; 
  signal c_FFd3 : STD_LOGIC; 
  signal c_FFd10 : STD_LOGIC; 
  signal CHOICE1 : STD_LOGIC; 
  signal CHOICE18 : STD_LOGIC; 
  signal c_FFd9 : STD_LOGIC; 
  signal c_FFd6 : STD_LOGIC; 
  signal c_FFd8 : STD_LOGIC; 
  signal CHOICE5 : STD_LOGIC; 
  signal CHOICE19 : STD_LOGIC; 
  signal clkdiv : STD_LOGIC; 
  signal Q_n0014 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal flag3 : STD_LOGIC; 
  signal c_FFd1 : STD_LOGIC; 
  signal c_FFd5 : STD_LOGIC; 
  signal c_FFd7 : STD_LOGIC; 
  signal CHOICE39 : STD_LOGIC; 
  signal CHOICE9 : STD_LOGIC; 
  signal flag1 : STD_LOGIC; 
  signal flag1_N69 : STD_LOGIC; 
  signal load_BUFGP : STD_LOGIC; 
  signal flag2 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal data_0_IBUF : STD_LOGIC; 
  signal data_1_IBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal data_2_IBUF : STD_LOGIC; 
  signal data_3_IBUF : STD_LOGIC; 
  signal data_4_IBUF : STD_LOGIC; 
  signal data_5_IBUF : STD_LOGIC; 
  signal data_6_IBUF : STD_LOGIC; 
  signal data_7_IBUF : STD_LOGIC; 
  signal busy_OBUF : STD_LOGIC; 
  signal t : STD_LOGIC; 
  signal load_BUFGP_IBUFG : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Q_n001739_O : STD_LOGIC; 
  signal Q_n001811_O : STD_LOGIC; 
  signal Q_n00148_O : STD_LOGIC; 
  signal Q_n001722_O : STD_LOGIC; 
  signal CHOICE13 : STD_LOGIC; 
  signal Q_n001712_O : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal CHOICE1_F : STD_LOGIC; 
  signal CHOICE1_G : STD_LOGIC; 
  signal CHOICE5_F : STD_LOGIC; 
  signal CHOICE5_G : STD_LOGIC; 
  signal clkdiv_DYMUX : STD_LOGIC; 
  signal clkdiv_BYINVNOT : STD_LOGIC; 
  signal clkdiv_CLKINV : STD_LOGIC; 
  signal clkdiv_CEINV : STD_LOGIC; 
  signal c_FFd2_DXMUX : STD_LOGIC; 
  signal c_FFd2_DYMUX : STD_LOGIC; 
  signal c_FFd2_CLKINV : STD_LOGIC; 
  signal c_FFd2_CEINV : STD_LOGIC; 
  signal c_FFd4_DXMUX : STD_LOGIC; 
  signal c_FFd4_DYMUX : STD_LOGIC; 
  signal c_FFd4_CLKINV : STD_LOGIC; 
  signal c_FFd4_CEINV : STD_LOGIC; 
  signal c_FFd6_DXMUX : STD_LOGIC; 
  signal c_FFd6_DYMUX : STD_LOGIC; 
  signal c_FFd6_CLKINV : STD_LOGIC; 
  signal c_FFd6_CEINV : STD_LOGIC; 
  signal c_FFd8_DXMUX : STD_LOGIC; 
  signal c_FFd8_DYMUX : STD_LOGIC; 
  signal c_FFd8_CLKINV : STD_LOGIC; 
  signal c_FFd8_CEINV : STD_LOGIC; 
  signal c_FFd10_DXMUX : STD_LOGIC; 
  signal c_FFd10_DYMUX : STD_LOGIC; 
  signal c_FFd10_CLKINV : STD_LOGIC; 
  signal c_FFd10_CEINV : STD_LOGIC; 
  signal CHOICE39_F : STD_LOGIC; 
  signal CHOICE9_F : STD_LOGIC; 
  signal flag1_F : STD_LOGIC; 
  signal flag1_DYMUX : STD_LOGIC; 
  signal flag1_G : STD_LOGIC; 
  signal flag1_BYINVNOT : STD_LOGIC; 
  signal flag1_CLKINV : STD_LOGIC; 
  signal flag1_CEINV : STD_LOGIC; 
  signal count_0_DXMUX : STD_LOGIC; 
  signal count_0_LOGIC_ONE : STD_LOGIC; 
  signal count_0_CYINIT : STD_LOGIC; 
  signal count_N433 : STD_LOGIC; 
  signal count_0_BXINVNOT : STD_LOGIC; 
  signal count_0_DYMUX : STD_LOGIC; 
  signal count_0_XORG : STD_LOGIC; 
  signal count_0_CYMUXG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal count_0_LOGIC_ZERO : STD_LOGIC; 
  signal count_0_G : STD_LOGIC; 
  signal count_0_SRINV : STD_LOGIC; 
  signal count_0_CLKINV : STD_LOGIC; 
  signal count_2_DXMUX : STD_LOGIC; 
  signal count_2_XORF : STD_LOGIC; 
  signal count_2_CYINIT : STD_LOGIC; 
  signal count_2_DYMUX : STD_LOGIC; 
  signal count_2_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal count_2_F : STD_LOGIC; 
  signal count_2_CYMUXFAST : STD_LOGIC; 
  signal count_2_CYAND : STD_LOGIC; 
  signal count_2_FASTCARRY : STD_LOGIC; 
  signal count_2_CYMUXG2 : STD_LOGIC; 
  signal count_2_CYMUXF2 : STD_LOGIC; 
  signal count_2_LOGIC_ZERO : STD_LOGIC; 
  signal count_2_G : STD_LOGIC; 
  signal count_2_SRINV : STD_LOGIC; 
  signal count_2_CLKINV : STD_LOGIC; 
  signal count_4_DXMUX : STD_LOGIC; 
  signal count_4_XORF : STD_LOGIC; 
  signal count_4_CYINIT : STD_LOGIC; 
  signal count_4_DYMUX : STD_LOGIC; 
  signal count_4_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal count_4_F : STD_LOGIC; 
  signal count_4_CYMUXFAST : STD_LOGIC; 
  signal count_4_CYAND : STD_LOGIC; 
  signal count_4_FASTCARRY : STD_LOGIC; 
  signal count_4_CYMUXG2 : STD_LOGIC; 
  signal count_4_CYMUXF2 : STD_LOGIC; 
  signal count_4_LOGIC_ZERO : STD_LOGIC; 
  signal count_4_G : STD_LOGIC; 
  signal count_4_SRINV : STD_LOGIC; 
  signal count_4_CLKINV : STD_LOGIC; 
  signal count_6_DXMUX : STD_LOGIC; 
  signal count_6_XORF : STD_LOGIC; 
  signal count_6_CYINIT : STD_LOGIC; 
  signal count_6_DYMUX : STD_LOGIC; 
  signal count_6_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal count_6_F : STD_LOGIC; 
  signal count_6_CYMUXFAST : STD_LOGIC; 
  signal count_6_CYAND : STD_LOGIC; 
  signal count_6_FASTCARRY : STD_LOGIC; 
  signal count_6_CYMUXG2 : STD_LOGIC; 
  signal count_6_CYMUXF2 : STD_LOGIC; 
  signal count_6_LOGIC_ZERO : STD_LOGIC; 
  signal count_6_G : STD_LOGIC; 
  signal count_6_SRINV : STD_LOGIC; 
  signal count_6_CLKINV : STD_LOGIC; 
  signal count_8_DXMUX : STD_LOGIC; 
  signal count_8_XORF : STD_LOGIC; 
  signal count_8_LOGIC_ZERO : STD_LOGIC; 
  signal count_8_CYINIT : STD_LOGIC; 
  signal count_8_F : STD_LOGIC; 
  signal count_8_DYMUX : STD_LOGIC; 
  signal count_8_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal count_9_rt : STD_LOGIC; 
  signal count_8_SRINV : STD_LOGIC; 
  signal count_8_CLKINV : STD_LOGIC; 
  signal data_0_INBUF_B : STD_LOGIC; 
  signal data_0_ENABLE : STD_LOGIC; 
  signal data_1_INBUF_B : STD_LOGIC; 
  signal data_1_ENABLE : STD_LOGIC; 
  signal clk_INBUF_B : STD_LOGIC; 
  signal clk_ENABLE : STD_LOGIC; 
  signal data_2_INBUF_B : STD_LOGIC; 
  signal data_2_ENABLE : STD_LOGIC; 
  signal data_3_INBUF_B : STD_LOGIC; 
  signal data_3_ENABLE : STD_LOGIC; 
  signal data_4_INBUF_B : STD_LOGIC; 
  signal data_4_ENABLE : STD_LOGIC; 
  signal data_5_INBUF_B : STD_LOGIC; 
  signal data_5_ENABLE : STD_LOGIC; 
  signal data_6_INBUF_B : STD_LOGIC; 
  signal data_6_ENABLE : STD_LOGIC; 
  signal clkdiv_FFY_RST : STD_LOGIC; 
  signal data_7_INBUF_B : STD_LOGIC; 
  signal data_7_ENABLE : STD_LOGIC; 
  signal busy_ENABLE : STD_LOGIC; 
  signal TXD_ENABLE : STD_LOGIC; 
  signal load_INBUF_B : STD_LOGIC; 
  signal load_ENABLE : STD_LOGIC; 
  signal databuffer_0_I1 : STD_LOGIC; 
  signal databuffer_0_DLYCE : STD_LOGIC; 
  signal databuffer_0_DLYRST : STD_LOGIC; 
  signal databuffer_0_DLYINC : STD_LOGIC; 
  signal databuffer_1_I1 : STD_LOGIC; 
  signal databuffer_1_DLYCE : STD_LOGIC; 
  signal databuffer_1_DLYRST : STD_LOGIC; 
  signal databuffer_1_DLYINC : STD_LOGIC; 
  signal databuffer_2_I1 : STD_LOGIC; 
  signal databuffer_2_DLYCE : STD_LOGIC; 
  signal databuffer_2_DLYRST : STD_LOGIC; 
  signal databuffer_2_DLYINC : STD_LOGIC; 
  signal databuffer_3_I1 : STD_LOGIC; 
  signal databuffer_3_DLYCE : STD_LOGIC; 
  signal databuffer_3_DLYRST : STD_LOGIC; 
  signal databuffer_3_DLYINC : STD_LOGIC; 
  signal databuffer_4_I1 : STD_LOGIC; 
  signal databuffer_4_DLYCE : STD_LOGIC; 
  signal databuffer_4_DLYRST : STD_LOGIC; 
  signal databuffer_4_DLYINC : STD_LOGIC; 
  signal databuffer_5_I1 : STD_LOGIC; 
  signal databuffer_5_DLYCE : STD_LOGIC; 
  signal databuffer_5_DLYRST : STD_LOGIC; 
  signal databuffer_5_DLYINC : STD_LOGIC; 
  signal databuffer_6_I1 : STD_LOGIC; 
  signal databuffer_6_DLYCE : STD_LOGIC; 
  signal databuffer_6_DLYRST : STD_LOGIC; 
  signal databuffer_6_DLYINC : STD_LOGIC; 
  signal databuffer_7_I1 : STD_LOGIC; 
  signal databuffer_7_DLYCE : STD_LOGIC; 
  signal databuffer_7_DLYRST : STD_LOGIC; 
  signal databuffer_7_DLYINC : STD_LOGIC; 
  signal busy_OBUF_C1INV : STD_LOGIC; 
  signal t_C1INV : STD_LOGIC; 
  signal c_FFd2_FFY_RST : STD_LOGIC; 
  signal flag2_DXMUX : STD_LOGIC; 
  signal Q_n001835_O : STD_LOGIC; 
  signal flag2_G : STD_LOGIC; 
  signal flag2_CLKINV : STD_LOGIC; 
  signal flag2_CEINV : STD_LOGIC; 
  signal Q_n0014_F : STD_LOGIC; 
  signal Q_n0014_G : STD_LOGIC; 
  signal CHOICE13_F : STD_LOGIC; 
  signal CHOICE13_G : STD_LOGIC; 
  signal Q_n001739_O_F : STD_LOGIC; 
  signal Q_n001739_O_G : STD_LOGIC; 
  signal c_FFd2_FFX_RST : STD_LOGIC; 
  signal c_FFd4_FFY_RST : STD_LOGIC; 
  signal c_FFd4_FFX_RST : STD_LOGIC; 
  signal c_FFd6_FFY_RST : STD_LOGIC; 
  signal c_FFd6_FFX_RST : STD_LOGIC; 
  signal c_FFd8_FFY_RST : STD_LOGIC; 
  signal c_FFd8_FFX_RST : STD_LOGIC; 
  signal c_FFd10_FFY_RST : STD_LOGIC; 
  signal c_FFd10_FFX_SET : STD_LOGIC; 
  signal flag1_FFY_RST : STD_LOGIC; 
  signal databuffer_0_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_0_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_1_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_1_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_0_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_0_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_0_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_2_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_2_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_1_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_1_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_1_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_7_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_7_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_6_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_6_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_6_IFF_CE1INV : STD_LOGIC; 
  signal busy_OBUF_OFF_OFF1 : STD_LOGIC; 
  signal busy_OBUF_OFF_OSRUSED : STD_LOGIC; 
  signal busy_OBUF_OFF_D1INV : STD_LOGIC; 
  signal databuffer_7_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_7_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_7_IFF_CE1INV : STD_LOGIC; 
  signal t_OFF_OFF1 : STD_LOGIC; 
  signal t_OFF_OCEINV : STD_LOGIC; 
  signal t_OFF_D1INV : STD_LOGIC; 
  signal t_OFF_OFF1_SET : STD_LOGIC; 
  signal databuffer_3_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_3_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_2_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_2_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_2_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_4_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_4_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_3_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_3_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_3_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_5_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_5_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal databuffer_4_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_4_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_4_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_5_IFF_IFF1 : STD_LOGIC; 
  signal databuffer_5_IFF_CLKINV : STD_LOGIC; 
  signal databuffer_5_IFF_CE1INV : STD_LOGIC; 
  signal databuffer_6_DELCHAIN_DELCH_OUT : STD_LOGIC; 
  signal databuffer_6_DELCHAIN_IDELAYMUX : STD_LOGIC; 
  signal flag2_FFX_RST : STD_LOGIC; 
  signal PWR_VCC_0_GND : STD_LOGIC; 
  signal PWR_VCC_1_GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NLW_DELCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_1_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_2_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_7_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_3_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_4_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_5_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_databuffer_6_DELCHAIN_DELAYCHAIN_C_UNCONNECTED : STD_LOGIC; 
  signal databuffer : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal count : STD_LOGIC_VECTOR ( 9 downto 0 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  Q_n00171 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => databuffer(7),
      ADR1 => VCC,
      ADR2 => c_FFd2,
      ADR3 => VCC,
      O => CHOICE1_F
    );
  Q_n00184 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd3,
      ADR1 => c_FFd4,
      ADR2 => c_FFd2,
      ADR3 => c_FFd10,
      O => CHOICE1_G
    );
  CHOICE1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE1_F,
      O => CHOICE1
    );
  CHOICE1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE1_G,
      O => CHOICE18
    );
  Q_n00185 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => c_FFd8,
      ADR1 => c_FFd9,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE5_G
    );
  CHOICE5_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE5_F,
      O => CHOICE5
    );
  CHOICE5_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE5_G,
      O => CHOICE19
    );
  clkdiv_DYMUX_0 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv_BYINVNOT,
      O => clkdiv_DYMUX
    );
  clkdiv_BYINV : X_INV
    port map (
      I => clkdiv,
      O => clkdiv_BYINVNOT
    );
  clkdiv_CLKINV_1 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => clkdiv_CLKINV
    );
  clkdiv_CEINV_2 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0014,
      O => clkdiv_CEINV
    );
  c_FFd2_DXMUX_3 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd3,
      O => c_FFd2_DXMUX
    );
  c_FFd2_DYMUX_4 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd2,
      O => c_FFd2_DYMUX
    );
  c_FFd2_CLKINV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd2_CLKINV
    );
  c_FFd2_CEINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => c_FFd2_CEINV
    );
  c_FFd4_DXMUX_7 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd5,
      O => c_FFd4_DXMUX
    );
  c_FFd4_DYMUX_8 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd4,
      O => c_FFd4_DYMUX
    );
  c_FFd4_CLKINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd4_CLKINV
    );
  c_FFd4_CEINV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => c_FFd4_CEINV
    );
  c_FFd6_DXMUX_11 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd7,
      O => c_FFd6_DXMUX
    );
  c_FFd6_DYMUX_12 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd6,
      O => c_FFd6_DYMUX
    );
  c_FFd6_CLKINV_13 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd6_CLKINV
    );
  c_FFd6_CEINV_14 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => c_FFd6_CEINV
    );
  c_FFd8_DXMUX_15 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd9,
      O => c_FFd8_DXMUX
    );
  c_FFd8_DYMUX_16 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd8,
      O => c_FFd8_DYMUX
    );
  c_FFd8_CLKINV_17 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd8_CLKINV
    );
  c_FFd8_CEINV_18 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => c_FFd8_CEINV
    );
  c_FFd10_DXMUX_19 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd1,
      O => c_FFd10_DXMUX
    );
  c_FFd10_DYMUX_20 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd10,
      O => c_FFd10_DYMUX
    );
  c_FFd10_CLKINV_21 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd10_CLKINV
    );
  c_FFd10_CEINV_22 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag3,
      O => c_FFd10_CEINV
    );
  CHOICE39_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE39_F,
      O => CHOICE39
    );
  Q_n001721 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => databuffer(4),
      ADR1 => databuffer(5),
      ADR2 => c_FFd4,
      ADR3 => c_FFd5,
      O => CHOICE9_F
    );
  CHOICE9_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE9_F,
      O => CHOICE9
    );
  Q_n00179 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => databuffer(0),
      ADR1 => c_FFd9,
      ADR2 => c_FFd6,
      ADR3 => databuffer(3),
      O => CHOICE5_F
    );
  flag1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_F,
      O => flag1_N69
    );
  flag1_DYMUX_23 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_BYINVNOT,
      O => flag1_DYMUX
    );
  flag1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_G,
      O => flag3
    );
  flag1_BYINV : X_INV
    port map (
      I => flag1,
      O => flag1_BYINVNOT
    );
  flag1_CLKINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => load_BUFGP,
      O => flag1_CLKINV
    );
  flag1_CEINV_25 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => flag1_N69,
      O => flag1_CEINV
    );
  count_0_LOGIC_ZERO_26 : X_ZERO
    port map (
      O => count_0_LOGIC_ZERO
    );
  count_0_LOGIC_ONE_27 : X_ONE
    port map (
      O => count_0_LOGIC_ONE
    );
  count_0_DXMUX_28 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (