new_top_timesim.vhd

自己在ISE下用VHDL写的UART

    );
  XLXI_1_count_6_LOGIC_ZERO_148 : X_ZERO
    port map (
      O => XLXI_1_count_6_LOGIC_ZERO
    );
  XLXI_1_count_6_DXMUX_149 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_6_XORF,
      O => XLXI_1_count_6_DXMUX
    );
  XLXI_1_count_6_XORF_150 : X_XOR2
    port map (
      I0 => XLXI_1_count_6_CYINIT,
      I1 => XLXI_1_count_6_F,
      O => XLXI_1_count_6_XORF
    );
  XLXI_1_count_6_CYMUXF : X_MUX2
    port map (
      IA => XLXI_1_count_6_LOGIC_ZERO,
      IB => XLXI_1_count_6_CYINIT,
      SEL => XLXI_1_count_6_F,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_6_cyo
    );
  XLXI_1_count_6_CYMUXF2_151 : X_MUX2
    port map (
      IA => XLXI_1_count_6_LOGIC_ZERO,
      IB => XLXI_1_count_6_LOGIC_ZERO,
      SEL => XLXI_1_count_6_F,
      O => XLXI_1_count_6_CYMUXF2
    );
  XLXI_1_count_6_CYINIT_152 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_5_cyo,
      O => XLXI_1_count_6_CYINIT
    );
  XLXI_1_count_6_DYMUX_153 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_6_XORG,
      O => XLXI_1_count_6_DYMUX
    );
  XLXI_1_count_6_XORG_154 : X_XOR2
    port map (
      I0 => XLXI_1_count_LPM_COUNTER_2_n0000_6_cyo,
      I1 => XLXI_1_count_6_G,
      O => XLXI_1_count_6_XORG
    );
  XLXI_1_count_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_6_CYMUXFAST,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_7_cyo
    );
  XLXI_1_count_6_FASTCARRY_155 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_5_cyo,
      O => XLXI_1_count_6_FASTCARRY
    );
  XLXI_1_count_6_CYAND_156 : X_AND2
    port map (
      I0 => XLXI_1_count_6_G,
      I1 => XLXI_1_count_6_F,
      O => XLXI_1_count_6_CYAND
    );
  XLXI_1_count_6_CYMUXFAST_157 : X_MUX2
    port map (
      IA => XLXI_1_count_6_CYMUXG2,
      IB => XLXI_1_count_6_FASTCARRY,
      SEL => XLXI_1_count_6_CYAND,
      O => XLXI_1_count_6_CYMUXFAST
    );
  XLXI_1_count_6_CYMUXG2_158 : X_MUX2
    port map (
      IA => XLXI_1_count_6_LOGIC_ZERO,
      IB => XLXI_1_count_6_CYMUXF2,
      SEL => XLXI_1_count_6_G,
      O => XLXI_1_count_6_CYMUXG2
    );
  XLXI_1_count_6_SRINV_159 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0015,
      O => XLXI_1_count_6_SRINV
    );
  XLXI_1_count_6_CLKINV_160 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_count_6_CLKINV
    );
  XLXI_1_count_6_CEINV_161 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_count_6_CEINV
    );
  XLXI_1_count_8_LOGIC_ZERO_162 : X_ZERO
    port map (
      O => XLXI_1_count_8_LOGIC_ZERO
    );
  XLXI_1_count_8_DXMUX_163 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_8_XORF,
      O => XLXI_1_count_8_DXMUX
    );
  XLXI_1_count_8_XORF_164 : X_XOR2
    port map (
      I0 => XLXI_1_count_8_CYINIT,
      I1 => XLXI_1_count_8_F,
      O => XLXI_1_count_8_XORF
    );
  XLXI_1_count_8_CYMUXF : X_MUX2
    port map (
      IA => XLXI_1_count_8_LOGIC_ZERO,
      IB => XLXI_1_count_8_CYINIT,
      SEL => XLXI_1_count_8_F,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_8_cyo
    );
  XLXI_1_count_8_CYINIT_165 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_7_cyo,
      O => XLXI_1_count_8_CYINIT
    );
  XLXI_1_count_8_DYMUX_166 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_8_XORG,
      O => XLXI_1_count_8_DYMUX
    );
  XLXI_1_count_8_XORG_167 : X_XOR2
    port map (
      I0 => XLXI_1_count_LPM_COUNTER_2_n0000_8_cyo,
      I1 => XLXI_1_count_9_rt,
      O => XLXI_1_count_8_XORG
    );
  XLXI_1_count_8_SRINV_168 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0015,
      O => XLXI_1_count_8_SRINV
    );
  XLXI_1_count_8_CLKINV_169 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_count_8_CLKINV
    );
  XLXI_1_count_8_CEINV_170 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_count_8_CEINV
    );
  clk100m_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_INBUF_B,
      O => clk100m_BUFGP_IBUFG
    );
  clk100m_BUFGP_IBUFG_171 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m,
      O => clk100m_INBUF_B
    );
  clk100m_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => clk100m_ENABLE
    );
  busy_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_busy,
      CTL => busy_ENABLE,
      O => busy
    );
  busy_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => busy_ENABLE
    );
  rxd_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => rxd_INBUF_B,
      O => rxd_BUFGP_IBUFG
    );
  rxd_BUFGP_IBUFG_172 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => rxd,
      O => rxd_INBUF_B
    );
  rxd_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => rxd_ENABLE
    );
  rst_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => rst_INBUF_B,
      O => rst_IBUF
    );
  rst_IBUF_173 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => rst,
      O => rst_INBUF_B
    );
  rst_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => rst_ENABLE
    );
  txd_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_t,
      CTL => txd_ENABLE,
      O => txd
    );
  txd_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => txd_ENABLE
    );
  XLXI_2_busy_CLK1INV : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_busy_C1INV
    );
  XLXI_2_c_FFd1_174 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_2_c_FFd2_DYMUX,
      CE => XLXI_2_c_FFd2_CEINV,
      CLK => XLXI_2_c_FFd2_CLKINV,
      SET => GND,
      RST => XLXI_2_c_FFd2_FFY_RST,
      O => XLXI_2_c_FFd1
    );
  XLXI_2_c_FFd2_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => XLXI_2_c_FFd2_FFY_RST
    );
  XLXI_2_t_CLK1INV : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_t_C1INV
    );
  XLXI_1_do_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_do_F,
      O => CHOICE643
    );
  XLXI_1_do_DYMUX_175 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n00171_O,
      O => XLXI_1_do_DYMUX
    );
  XLXI_1_do_SRINV_176 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f1_N292,
      O => XLXI_1_do_SRINV
    );
  XLXI_1_do_CLKINV_177 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_clkdiv,
      O => XLXI_1_do_CLKINV
    );
  XLXI_1_n001322 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => XLXI_1_count(0),
      ADR1 => XLXI_1_count(1),
      ADR2 => XLXI_1_count(9),
      ADR3 => XLXI_1_count(8),
      O => XLXI_1_n0013_G
    );
  XLXI_1_n0013_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0013_F,
      O => XLXI_1_n0013
    );
  XLXI_1_n0013_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0013_G,
      O => CHOICE703
    );
  XLXI_2_databuffer_1_DXMUX_178 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_tmp_data(1),
      O => XLXI_2_databuffer_1_DXMUX
    );
  XLXI_2_databuffer_1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_databuffer_1_F,
      O => XLXI_2_flag3
    );
  XLXI_2_databuffer_1_DYMUX_179 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_tmp_data(0),
      O => XLXI_2_databuffer_1_DYMUX
    );
  XLXI_2_databuffer_1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_databuffer_1_G,
      O => XLXI_2_busy_N302
    );
  XLXI_2_databuffer_1_CLKINV_180 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_t3,
      O => XLXI_2_databuffer_1_CLKINV
    );
  XLXI_2_databuffer_1_CEINV_181 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_busy_N302,
      O => XLXI_2_databuffer_1_CEINV
    );
  XLXI_2_n00148 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => XLXI_2_count(2),
      ADR1 => XLXI_2_count(3),
      ADR2 => XLXI_2_count(5),
      ADR3 => XLXI_2_count(4),
      O => XLXI_2_n0014_G
    );
  XLXI_2_n0014_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014_F,
      O => XLXI_2_n0014
    );
  XLXI_2_n0014_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014_G,
      O => XLXI_2_n00148_O
    );
  XLXI_2_flag2_DXMUX_182 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n001835_O,
      O => XLXI_2_flag2_DXMUX
    );
  XLXI_2_flag2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag2_G,
      O => XLXI_2_n001811_O
    );
  XLXI_2_flag2_CLKINV_183 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_flag2_CLKINV
    );
  XLXI_2_flag2_CEINV_184 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_flag2_CEINV
    );
  XLXI_1_n0015_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    por