new_top_timesim.vhd

自己在ISE下用VHDL写的UART

  XLXI_2_count_6_LOGIC_ZERO_89 : X_ZERO
    port map (
      O => XLXI_2_count_6_LOGIC_ZERO
    );
  XLXI_2_count_6_DXMUX_90 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_6_XORF,
      O => XLXI_2_count_6_DXMUX
    );
  XLXI_2_count_6_XORF_91 : X_XOR2
    port map (
      I0 => XLXI_2_count_6_CYINIT,
      I1 => XLXI_2_count_6_F,
      O => XLXI_2_count_6_XORF
    );
  XLXI_2_count_6_CYMUXF : X_MUX2
    port map (
      IA => XLXI_2_count_6_LOGIC_ZERO,
      IB => XLXI_2_count_6_CYINIT,
      SEL => XLXI_2_count_6_F,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_6_cyo
    );
  XLXI_2_count_6_CYMUXF2_92 : X_MUX2
    port map (
      IA => XLXI_2_count_6_LOGIC_ZERO,
      IB => XLXI_2_count_6_LOGIC_ZERO,
      SEL => XLXI_2_count_6_F,
      O => XLXI_2_count_6_CYMUXF2
    );
  XLXI_2_count_6_CYINIT_93 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_5_cyo,
      O => XLXI_2_count_6_CYINIT
    );
  XLXI_2_count_6_DYMUX_94 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_6_XORG,
      O => XLXI_2_count_6_DYMUX
    );
  XLXI_2_count_6_XORG_95 : X_XOR2
    port map (
      I0 => XLXI_2_count_LPM_COUNTER_1_n0000_6_cyo,
      I1 => XLXI_2_count_6_G,
      O => XLXI_2_count_6_XORG
    );
  XLXI_2_count_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_6_CYMUXFAST,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_7_cyo
    );
  XLXI_2_count_6_FASTCARRY_96 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_5_cyo,
      O => XLXI_2_count_6_FASTCARRY
    );
  XLXI_2_count_6_CYAND_97 : X_AND2
    port map (
      I0 => XLXI_2_count_6_G,
      I1 => XLXI_2_count_6_F,
      O => XLXI_2_count_6_CYAND
    );
  XLXI_2_count_6_CYMUXFAST_98 : X_MUX2
    port map (
      IA => XLXI_2_count_6_CYMUXG2,
      IB => XLXI_2_count_6_FASTCARRY,
      SEL => XLXI_2_count_6_CYAND,
      O => XLXI_2_count_6_CYMUXFAST
    );
  XLXI_2_count_6_CYMUXG2_99 : X_MUX2
    port map (
      IA => XLXI_2_count_6_LOGIC_ZERO,
      IB => XLXI_2_count_6_CYMUXF2,
      SEL => XLXI_2_count_6_G,
      O => XLXI_2_count_6_CYMUXG2
    );
  XLXI_2_count_6_SRINV_100 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_count_6_SRINV
    );
  XLXI_2_count_6_CLKINV_101 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_count_6_CLKINV
    );
  XLXI_2_count_8_LOGIC_ZERO_102 : X_ZERO
    port map (
      O => XLXI_2_count_8_LOGIC_ZERO
    );
  XLXI_2_count_8_DXMUX_103 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_8_XORF,
      O => XLXI_2_count_8_DXMUX
    );
  XLXI_2_count_8_XORF_104 : X_XOR2
    port map (
      I0 => XLXI_2_count_8_CYINIT,
      I1 => XLXI_2_count_8_F,
      O => XLXI_2_count_8_XORF
    );
  XLXI_2_count_8_CYMUXF : X_MUX2
    port map (
      IA => XLXI_2_count_8_LOGIC_ZERO,
      IB => XLXI_2_count_8_CYINIT,
      SEL => XLXI_2_count_8_F,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_8_cyo
    );
  XLXI_2_count_8_CYINIT_105 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_7_cyo,
      O => XLXI_2_count_8_CYINIT
    );
  XLXI_2_count_8_DYMUX_106 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_8_XORG,
      O => XLXI_2_count_8_DYMUX
    );
  XLXI_2_count_8_XORG_107 : X_XOR2
    port map (
      I0 => XLXI_2_count_LPM_COUNTER_1_n0000_8_cyo,
      I1 => XLXI_2_count_9_rt,
      O => XLXI_2_count_8_XORG
    );
  XLXI_2_count_8_SRINV_108 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_count_8_SRINV
    );
  XLXI_2_count_8_CLKINV_109 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_count_8_CLKINV
    );
  XLXI_1_count_0_LOGIC_ZERO_110 : X_ZERO
    port map (
      O => XLXI_1_count_0_LOGIC_ZERO
    );
  XLXI_1_count_0_LOGIC_ONE_111 : X_ONE
    port map (
      O => XLXI_1_count_0_LOGIC_ONE
    );
  XLXI_1_count_0_DXMUX_112 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_N1307,
      O => XLXI_1_count_0_DXMUX
    );
  XLXI_1_count_0_CYMUXF : X_MUX2
    port map (
      IA => XLXI_1_count_0_LOGIC_ONE,
      IB => XLXI_1_count_0_CYINIT,
      SEL => XLXI_1_count_N1307,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_0_cyo
    );
  XLXI_1_count_0_CYINIT_113 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_0_BXINVNOT,
      O => XLXI_1_count_0_CYINIT
    );
  XLXI_1_count_0_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => XLXI_1_count_0_BXINVNOT
    );
  XLXI_1_count_0_DYMUX_114 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_0_XORG,
      O => XLXI_1_count_0_DYMUX
    );
  XLXI_1_count_0_XORG_115 : X_XOR2
    port map (
      I0 => XLXI_1_count_LPM_COUNTER_2_n0000_0_cyo,
      I1 => XLXI_1_count_0_G,
      O => XLXI_1_count_0_XORG
    );
  XLXI_1_count_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_0_CYMUXG,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_1_cyo
    );
  XLXI_1_count_0_CYMUXG_116 : X_MUX2
    port map (
      IA => XLXI_1_count_0_LOGIC_ZERO,
      IB => XLXI_1_count_LPM_COUNTER_2_n0000_0_cyo,
      SEL => XLXI_1_count_0_G,
      O => XLXI_1_count_0_CYMUXG
    );
  XLXI_1_count_0_SRINV_117 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0015,
      O => XLXI_1_count_0_SRINV
    );
  XLXI_1_count_0_CLKINV_118 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_count_0_CLKINV
    );
  XLXI_1_count_0_CEINV_119 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_count_0_CEINV
    );
  XLXI_1_count_2_LOGIC_ZERO_120 : X_ZERO
    port map (
      O => XLXI_1_count_2_LOGIC_ZERO
    );
  XLXI_1_count_2_DXMUX_121 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_2_XORF,
      O => XLXI_1_count_2_DXMUX
    );
  XLXI_1_count_2_XORF_122 : X_XOR2
    port map (
      I0 => XLXI_1_count_2_CYINIT,
      I1 => XLXI_1_count_2_F,
      O => XLXI_1_count_2_XORF
    );
  XLXI_1_count_2_CYMUXF : X_MUX2
    port map (
      IA => XLXI_1_count_2_LOGIC_ZERO,
      IB => XLXI_1_count_2_CYINIT,
      SEL => XLXI_1_count_2_F,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_2_cyo
    );
  XLXI_1_count_2_CYMUXF2_123 : X_MUX2
    port map (
      IA => XLXI_1_count_2_LOGIC_ZERO,
      IB => XLXI_1_count_2_LOGIC_ZERO,
      SEL => XLXI_1_count_2_F,
      O => XLXI_1_count_2_CYMUXF2
    );
  XLXI_1_count_2_CYINIT_124 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_1_cyo,
      O => XLXI_1_count_2_CYINIT
    );
  XLXI_1_count_2_DYMUX_125 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_2_XORG,
      O => XLXI_1_count_2_DYMUX
    );
  XLXI_1_count_2_XORG_126 : X_XOR2
    port map (
      I0 => XLXI_1_count_LPM_COUNTER_2_n0000_2_cyo,
      I1 => XLXI_1_count_2_G,
      O => XLXI_1_count_2_XORG
    );
  XLXI_1_count_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_2_CYMUXFAST,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_3_cyo
    );
  XLXI_1_count_2_FASTCARRY_127 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_1_cyo,
      O => XLXI_1_count_2_FASTCARRY
    );
  XLXI_1_count_2_CYAND_128 : X_AND2
    port map (
      I0 => XLXI_1_count_2_G,
      I1 => XLXI_1_count_2_F,
      O => XLXI_1_count_2_CYAND
    );
  XLXI_1_count_2_CYMUXFAST_129 : X_MUX2
    port map (
      IA => XLXI_1_count_2_CYMUXG2,
      IB => XLXI_1_count_2_FASTCARRY,
      SEL => XLXI_1_count_2_CYAND,
      O => XLXI_1_count_2_CYMUXFAST
    );
  XLXI_1_count_2_CYMUXG2_130 : X_MUX2
    port map (
      IA => XLXI_1_count_2_LOGIC_ZERO,
      IB => XLXI_1_count_2_CYMUXF2,
      SEL => XLXI_1_count_2_G,
      O => XLXI_1_count_2_CYMUXG2
    );
  XLXI_1_count_2_SRINV_131 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0015,
      O => XLXI_1_count_2_SRINV
    );
  XLXI_1_count_2_CLKINV_132 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_count_2_CLKINV
    );
  XLXI_1_count_2_CEINV_133 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_count_2_CEINV
    );
  XLXI_1_count_4_LOGIC_ZERO_134 : X_ZERO
    port map (
      O => XLXI_1_count_4_LOGIC_ZERO
    );
  XLXI_1_count_4_DXMUX_135 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_4_XORF,
      O => XLXI_1_count_4_DXMUX
    );
  XLXI_1_count_4_XORF_136 : X_XOR2
    port map (
      I0 => XLXI_1_count_4_CYINIT,
      I1 => XLXI_1_count_4_F,
      O => XLXI_1_count_4_XORF
    );
  XLXI_1_count_4_CYMUXF : X_MUX2
    port map (
      IA => XLXI_1_count_4_LOGIC_ZERO,
      IB => XLXI_1_count_4_CYINIT,
      SEL => XLXI_1_count_4_F,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_4_cyo
    );
  XLXI_1_count_4_CYMUXF2_137 : X_MUX2
    port map (
      IA => XLXI_1_count_4_LOGIC_ZERO,
      IB => XLXI_1_count_4_LOGIC_ZERO,
      SEL => XLXI_1_count_4_F,
      O => XLXI_1_count_4_CYMUXF2
    );
  XLXI_1_count_4_CYINIT_138 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_3_cyo,
      O => XLXI_1_count_4_CYINIT
    );
  XLXI_1_count_4_DYMUX_139 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_4_XORG,
      O => XLXI_1_count_4_DYMUX
    );
  XLXI_1_count_4_XORG_140 : X_XOR2
    port map (
      I0 => XLXI_1_count_LPM_COUNTER_2_n0000_4_cyo,
      I1 => XLXI_1_count_4_G,
      O => XLXI_1_count_4_XORG
    );
  XLXI_1_count_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_4_CYMUXFAST,
      O => XLXI_1_count_LPM_COUNTER_2_n0000_5_cyo
    );
  XLXI_1_count_4_FASTCARRY_141 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_count_LPM_COUNTER_2_n0000_3_cyo,
      O => XLXI_1_count_4_FASTCARRY
    );
  XLXI_1_count_4_CYAND_142 : X_AND2
    port map (
      I0 => XLXI_1_count_4_G,
      I1 => XLXI_1_count_4_F,
      O => XLXI_1_count_4_CYAND
    );
  XLXI_1_count_4_CYMUXFAST_143 : X_MUX2
    port map (
      IA => XLXI_1_count_4_CYMUXG2,
      IB => XLXI_1_count_4_FASTCARRY,
      SEL => XLXI_1_count_4_CYAND,
      O => XLXI_1_count_4_CYMUXFAST
    );
  XLXI_1_count_4_CYMUXG2_144 : X_MUX2
    port map (
      IA => XLXI_1_count_4_LOGIC_ZERO,
      IB => XLXI_1_count_4_CYMUXF2,
      SEL => XLXI_1_count_4_G,
      O => XLXI_1_count_4_CYMUXG2
    );
  XLXI_1_count_4_SRINV_145 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0015,
      O => XLXI_1_count_4_SRINV
    );
  XLXI_1_count_4_CLKINV_146 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_count_4_CLKINV
    );
  XLXI_1_count_4_CEINV_147 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_count_4_CEINV