new_top_timesim.vhd

自己在ISE下用VHDL写的UART

      O => XLXI_1_f1_N292
    );
  XLXI_1_clkdiv1_DYMUX_41 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_clkdiv1_BYINVNOT,
      O => XLXI_1_clkdiv1_DYMUX
    );
  XLXI_1_clkdiv1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_clkdiv1_G,
      O => XLXI_1_f3
    );
  XLXI_1_clkdiv1_BYINV : X_INV
    port map (
      I => XLXI_1_clkdiv,
      O => XLXI_1_clkdiv1_BYINVNOT
    );
  XLXI_1_clkdiv1_SRINV_42 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f1_N292,
      O => XLXI_1_clkdiv1_SRINV
    );
  XLXI_1_clkdiv1_CLKINV_43 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_1_clkdiv1_CLKINV
    );
  XLXI_1_clkdiv1_CEINV_44 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n0013,
      O => XLXI_1_clkdiv1_CEINV
    );
  XLXI_1_data_2_DXMUX_45 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_n001913_O,
      O => XLXI_1_data_2_DXMUX
    );
  XLXI_1_data_2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data_2_G,
      O => CHOICE627
    );
  XLXI_1_data_2_CLKINV_46 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_clkdiv,
      O => XLXI_1_data_2_CLKINV
    );
  XLXI_1_data_2_CEINV_47 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_f3,
      O => XLXI_1_data_2_CEINV
    );
  XLXI_3_t2_DXMUX_48 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_t1,
      O => XLXI_3_t2_DXMUX
    );
  XLXI_3_t2_DYMUX_49 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_tmp_load,
      O => XLXI_3_t2_DYMUX
    );
  XLXI_3_t2_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_t2_SRINVNOT
    );
  XLXI_3_t2_CLKINV_50 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_t2_CLKINV
    );
  XLXI_3_t3_DYMUX_51 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_t2,
      O => XLXI_3_t3_DYMUX
    );
  XLXI_3_t3_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_t3_SRINVNOT
    );
  XLXI_3_t3_CLKINV_52 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_t3_CLKINV
    );
  XLXI_2_n00171 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => XLXI_2_c_FFd2,
      ADR2 => VCC,
      ADR3 => XLXI_2_databuffer(7),
      O => CHOICE657_G
    );
  CHOICE657_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE657_F,
      O => CHOICE657
    );
  CHOICE657_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE657_G,
      O => CHOICE604
    );
  CHOICE608_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE608_F,
      O => CHOICE608
    );
  CHOICE608_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE608_G,
      O => CHOICE658
    );
  XLXI_2_count_0_LOGIC_ZERO_53 : X_ZERO
    port map (
      O => XLXI_2_count_0_LOGIC_ZERO
    );
  XLXI_2_count_0_LOGIC_ONE_54 : X_ONE
    port map (
      O => XLXI_2_count_0_LOGIC_ONE
    );
  XLXI_2_count_0_DXMUX_55 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_N1334,
      O => XLXI_2_count_0_DXMUX
    );
  XLXI_2_count_0_CYMUXF : X_MUX2
    port map (
      IA => XLXI_2_count_0_LOGIC_ONE,
      IB => XLXI_2_count_0_CYINIT,
      SEL => XLXI_2_count_N1334,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_0_cyo
    );
  XLXI_2_count_0_CYINIT_56 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_0_BXINVNOT,
      O => XLXI_2_count_0_CYINIT
    );
  XLXI_2_count_0_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_1,
      O => XLXI_2_count_0_BXINVNOT
    );
  XLXI_2_count_0_DYMUX_57 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_0_XORG,
      O => XLXI_2_count_0_DYMUX
    );
  XLXI_2_count_0_XORG_58 : X_XOR2
    port map (
      I0 => XLXI_2_count_LPM_COUNTER_1_n0000_0_cyo,
      I1 => XLXI_2_count_0_G,
      O => XLXI_2_count_0_XORG
    );
  XLXI_2_count_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_0_CYMUXG,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_1_cyo
    );
  XLXI_2_count_0_CYMUXG_59 : X_MUX2
    port map (
      IA => XLXI_2_count_0_LOGIC_ZERO,
      IB => XLXI_2_count_LPM_COUNTER_1_n0000_0_cyo,
      SEL => XLXI_2_count_0_G,
      O => XLXI_2_count_0_CYMUXG
    );
  XLXI_2_count_0_SRINV_60 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_count_0_SRINV
    );
  XLXI_2_count_0_CLKINV_61 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_count_0_CLKINV
    );
  XLXI_2_count_2_LOGIC_ZERO_62 : X_ZERO
    port map (
      O => XLXI_2_count_2_LOGIC_ZERO
    );
  XLXI_2_count_2_DXMUX_63 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_2_XORF,
      O => XLXI_2_count_2_DXMUX
    );
  XLXI_2_count_2_XORF_64 : X_XOR2
    port map (
      I0 => XLXI_2_count_2_CYINIT,
      I1 => XLXI_2_count_2_F,
      O => XLXI_2_count_2_XORF
    );
  XLXI_2_count_2_CYMUXF : X_MUX2
    port map (
      IA => XLXI_2_count_2_LOGIC_ZERO,
      IB => XLXI_2_count_2_CYINIT,
      SEL => XLXI_2_count_2_F,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_2_cyo
    );
  XLXI_2_count_2_CYMUXF2_65 : X_MUX2
    port map (
      IA => XLXI_2_count_2_LOGIC_ZERO,
      IB => XLXI_2_count_2_LOGIC_ZERO,
      SEL => XLXI_2_count_2_F,
      O => XLXI_2_count_2_CYMUXF2
    );
  XLXI_2_count_2_CYINIT_66 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_1_cyo,
      O => XLXI_2_count_2_CYINIT
    );
  XLXI_2_count_2_DYMUX_67 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_2_XORG,
      O => XLXI_2_count_2_DYMUX
    );
  XLXI_2_count_2_XORG_68 : X_XOR2
    port map (
      I0 => XLXI_2_count_LPM_COUNTER_1_n0000_2_cyo,
      I1 => XLXI_2_count_2_G,
      O => XLXI_2_count_2_XORG
    );
  XLXI_2_count_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_2_CYMUXFAST,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_3_cyo
    );
  XLXI_2_count_2_FASTCARRY_69 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_1_cyo,
      O => XLXI_2_count_2_FASTCARRY
    );
  XLXI_2_count_2_CYAND_70 : X_AND2
    port map (
      I0 => XLXI_2_count_2_G,
      I1 => XLXI_2_count_2_F,
      O => XLXI_2_count_2_CYAND
    );
  XLXI_2_count_2_CYMUXFAST_71 : X_MUX2
    port map (
      IA => XLXI_2_count_2_CYMUXG2,
      IB => XLXI_2_count_2_FASTCARRY,
      SEL => XLXI_2_count_2_CYAND,
      O => XLXI_2_count_2_CYMUXFAST
    );
  XLXI_2_count_2_CYMUXG2_72 : X_MUX2
    port map (
      IA => XLXI_2_count_2_LOGIC_ZERO,
      IB => XLXI_2_count_2_CYMUXF2,
      SEL => XLXI_2_count_2_G,
      O => XLXI_2_count_2_CYMUXG2
    );
  XLXI_2_count_2_SRINV_73 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_count_2_SRINV
    );
  XLXI_2_count_2_CLKINV_74 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_count_2_CLKINV
    );
  XLXI_2_clkdiv_75 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_2_clkdiv_DYMUX,
      CE => XLXI_2_clkdiv_CEINV,
      CLK => XLXI_2_clkdiv_CLKINV,
      SET => GND,
      RST => XLXI_2_clkdiv_FFY_RST,
      O => XLXI_2_clkdiv
    );
  XLXI_2_clkdiv_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => XLXI_2_clkdiv_FFY_RST
    );
  XLXI_2_count_4_LOGIC_ZERO_76 : X_ZERO
    port map (
      O => XLXI_2_count_4_LOGIC_ZERO
    );
  XLXI_2_count_4_DXMUX_77 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_4_XORF,
      O => XLXI_2_count_4_DXMUX
    );
  XLXI_2_count_4_XORF_78 : X_XOR2
    port map (
      I0 => XLXI_2_count_4_CYINIT,
      I1 => XLXI_2_count_4_F,
      O => XLXI_2_count_4_XORF
    );
  XLXI_2_count_4_CYMUXF : X_MUX2
    port map (
      IA => XLXI_2_count_4_LOGIC_ZERO,
      IB => XLXI_2_count_4_CYINIT,
      SEL => XLXI_2_count_4_F,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_4_cyo
    );
  XLXI_2_count_4_CYMUXF2_79 : X_MUX2
    port map (
      IA => XLXI_2_count_4_LOGIC_ZERO,
      IB => XLXI_2_count_4_LOGIC_ZERO,
      SEL => XLXI_2_count_4_F,
      O => XLXI_2_count_4_CYMUXF2
    );
  XLXI_2_count_4_CYINIT_80 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_3_cyo,
      O => XLXI_2_count_4_CYINIT
    );
  XLXI_2_count_4_DYMUX_81 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_4_XORG,
      O => XLXI_2_count_4_DYMUX
    );
  XLXI_2_count_4_XORG_82 : X_XOR2
    port map (
      I0 => XLXI_2_count_LPM_COUNTER_1_n0000_4_cyo,
      I1 => XLXI_2_count_4_G,
      O => XLXI_2_count_4_XORG
    );
  XLXI_2_count_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_4_CYMUXFAST,
      O => XLXI_2_count_LPM_COUNTER_1_n0000_5_cyo
    );
  XLXI_2_count_4_FASTCARRY_83 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_count_LPM_COUNTER_1_n0000_3_cyo,
      O => XLXI_2_count_4_FASTCARRY
    );
  XLXI_2_count_4_CYAND_84 : X_AND2
    port map (
      I0 => XLXI_2_count_4_G,
      I1 => XLXI_2_count_4_F,
      O => XLXI_2_count_4_CYAND
    );
  XLXI_2_count_4_CYMUXFAST_85 : X_MUX2
    port map (
      IA => XLXI_2_count_4_CYMUXG2,
      IB => XLXI_2_count_4_FASTCARRY,
      SEL => XLXI_2_count_4_CYAND,
      O => XLXI_2_count_4_CYMUXFAST
    );
  XLXI_2_count_4_CYMUXG2_86 : X_MUX2
    port map (
      IA => XLXI_2_count_4_LOGIC_ZERO,
      IB => XLXI_2_count_4_CYMUXF2,
      SEL => XLXI_2_count_4_G,
      O => XLXI_2_count_4_CYMUXG2
    );
  XLXI_2_count_4_SRINV_87 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_count_4_SRINV
    );
  XLXI_2_count_4_CLKINV_88 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_count_4_CLKINV
    );