new_top_timesim.vhd

自己在ISE下用VHDL写的UART

  signal XLXI_3_d2_DYMUX : STD_LOGIC; 
  signal XLXI_3_d2_CLKINV : STD_LOGIC; 
  signal XLXI_2_c_FFd4_FFY_RST : STD_LOGIC; 
  signal XLXI_1_f1_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd8_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd8_FFX_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd10_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd10_FFX_SET : STD_LOGIC; 
  signal XLXI_3_d2_FFY_RST : STD_LOGIC; 
  signal XLXI_3_d2_FFX_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_7_FFX_RST : STD_LOGIC; 
  signal XLXI_1_data_2_FFX_RST : STD_LOGIC; 
  signal XLXI_3_t2_FFY_RST : STD_LOGIC; 
  signal XLXI_3_t2_FFX_RST : STD_LOGIC; 
  signal XLXI_2_busy_OFF_OFF1 : STD_LOGIC; 
  signal XLXI_2_busy_OFF_OSRUSED : STD_LOGIC; 
  signal XLXI_2_busy_OFF_D1INV : STD_LOGIC; 
  signal XLXI_2_t_OFF_OFF1 : STD_LOGIC; 
  signal XLXI_2_t_OFF_OCEINV : STD_LOGIC; 
  signal XLXI_2_t_OFF_D1INV : STD_LOGIC; 
  signal XLXI_2_t_OFF_OFF1_SET : STD_LOGIC; 
  signal XLXI_1_data_0_FFY_RST : STD_LOGIC; 
  signal XLXI_1_data_0_FFX_RST : STD_LOGIC; 
  signal XLXI_2_databuffer_3_FFY_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_3_FFX_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_5_FFY_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_5_FFX_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_7_FFY_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_1_FFY_SET : STD_LOGIC; 
  signal XLXI_2_databuffer_1_FFX_SET : STD_LOGIC; 
  signal XLXI_2_flag2_FFX_RST : STD_LOGIC; 
  signal XLXI_1_data_1_FFX_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_1_FFX_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_3_FFY_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_3_FFX_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_5_FFY_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_5_FFX_RST : STD_LOGIC; 
  signal XLXI_3_tmp_data_7_FFY_RST : STD_LOGIC; 
  signal XLXI_3_t3_FFY_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd4_FFX_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd6_FFX_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd8_FFY_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd8_FFX_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd10_FFY_RST : STD_LOGIC; 
  signal XLXI_2_c_FFd10_FFX_SET : STD_LOGIC; 
  signal XLXI_3_tmp_data_1_FFY_RST : STD_LOGIC; 
  signal XLXI_2_databuffer_7_FFX_SET : STD_LOGIC; 
  signal XLXI_1_data_3_FFX_RST : STD_LOGIC; 
  signal XLXI_2_flag1_FFY_RST : STD_LOGIC; 
  signal XLXI_1_data_7_FFX_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd2_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd2_FFX_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd4_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd4_FFX_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd6_FFY_RST : STD_LOGIC; 
  signal XLXI_1_c_FFd6_FFX_RST : STD_LOGIC; 
  signal XLXI_1_data_4_FFX_RST : STD_LOGIC; 
  signal XLXI_1_data_5_FFX_RST : STD_LOGIC; 
  signal XLXI_1_data_6_FFX_RST : STD_LOGIC; 
  signal PWR_VCC_0_GND : STD_LOGIC; 
  signal PWR_VCC_1_GND : STD_LOGIC; 
  signal PWR_VCC_2_GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal XLXI_1_data : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_3_tmp_data : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_databuffer : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_count : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal XLXI_1_count : STD_LOGIC_VECTOR ( 9 downto 0 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  XLXI_1_n0016_SW10 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => rxd_BUFGP,
      ADR1 => VCC,
      ADR2 => XLXI_1_c_FFd9,
      ADR3 => VCC,
      O => CHOICE667_G
    );
  CHOICE667_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE667_F,
      O => CHOICE667
    );
  CHOICE667_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE667_G,
      O => CHOICE594
    );
  XLXI_2_clkdiv_DYMUX_0 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv_BYINVNOT,
      O => XLXI_2_clkdiv_DYMUX
    );
  XLXI_2_clkdiv_BYINV : X_INV
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_clkdiv_BYINVNOT
    );
  XLXI_2_clkdiv_CLKINV_1 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_2_clkdiv_CLKINV
    );
  XLXI_2_clkdiv_CEINV_2 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_n0014,
      O => XLXI_2_clkdiv_CEINV
    );
  XLXI_2_c_FFd2_DXMUX_3 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd3,
      O => XLXI_2_c_FFd2_DXMUX
    );
  XLXI_2_c_FFd2_DYMUX_4 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd2,
      O => XLXI_2_c_FFd2_DYMUX
    );
  XLXI_2_c_FFd2_CLKINV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_c_FFd2_CLKINV
    );
  XLXI_2_c_FFd2_CEINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_c_FFd2_CEINV
    );
  XLXI_3_tmp_load_DXMUX_7 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_n0004,
      O => XLXI_3_tmp_load_DXMUX
    );
  XLXI_3_tmp_load_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_tmp_load_G,
      O => XLXI_3_d3
    );
  XLXI_3_tmp_load_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_tmp_load_SRINVNOT
    );
  XLXI_3_tmp_load_CLKINV_8 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_tmp_load_CLKINV
    );
  XLXI_2_c_FFd4_DXMUX_9 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd5,
      O => XLXI_2_c_FFd4_DXMUX
    );
  XLXI_2_c_FFd4_DYMUX_10 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd4,
      O => XLXI_2_c_FFd4_DYMUX
    );
  XLXI_2_c_FFd4_CLKINV_11 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_c_FFd4_CLKINV
    );
  XLXI_2_c_FFd4_CEINV_12 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_c_FFd4_CEINV
    );
  XLXI_1_n00180 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => rxd_BUFGP,
      ADR1 => VCC,
      ADR2 => XLXI_1_c_FFd8,
      ADR3 => VCC,
      O => CHOICE667_F
    );
  XLXI_2_c_FFd6_DXMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd7,
      O => XLXI_2_c_FFd6_DXMUX
    );
  XLXI_2_c_FFd6_DYMUX_14 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd6,
      O => XLXI_2_c_FFd6_DYMUX
    );
  XLXI_2_c_FFd6_CLKINV_15 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_c_FFd6_CLKINV
    );
  XLXI_2_c_FFd6_CEINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_c_FFd6_CEINV
    );
  XLXI_2_c_FFd8_DXMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd9,
      O => XLXI_2_c_FFd8_DXMUX
    );
  XLXI_2_c_FFd8_DYMUX_18 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd8,
      O => XLXI_2_c_FFd8_DYMUX
    );
  XLXI_2_c_FFd8_CLKINV_19 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_c_FFd8_CLKINV
    );
  XLXI_2_c_FFd8_CEINV_20 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_c_FFd8_CEINV
    );
  XLXI_2_c_FFd10_DXMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd1,
      O => XLXI_2_c_FFd10_DXMUX
    );
  XLXI_2_c_FFd10_DYMUX_22 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_c_FFd10,
      O => XLXI_2_c_FFd10_DYMUX
    );
  XLXI_2_c_FFd10_CLKINV_23 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_clkdiv,
      O => XLXI_2_c_FFd10_CLKINV
    );
  XLXI_2_c_FFd10_CEINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_2_flag3,
      O => XLXI_2_c_FFd10_CEINV
    );
  XLXI_3_tmp_data_1_DXMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(1),
      O => XLXI_3_tmp_data_1_DXMUX
    );
  XLXI_3_tmp_data_1_DYMUX_26 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(0),
      O => XLXI_3_tmp_data_1_DYMUX
    );
  XLXI_3_tmp_data_1_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_tmp_data_1_SRINVNOT
    );
  XLXI_3_tmp_data_1_CLKINV_27 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_tmp_data_1_CLKINV
    );
  XLXI_3_tmp_data_1_CEINV_28 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_d3,
      O => XLXI_3_tmp_data_1_CEINV
    );
  XLXI_3_tmp_data_3_DXMUX_29 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(3),
      O => XLXI_3_tmp_data_3_DXMUX
    );
  XLXI_3_tmp_data_3_DYMUX_30 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(2),
      O => XLXI_3_tmp_data_3_DYMUX
    );
  XLXI_3_tmp_data_3_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_tmp_data_3_SRINVNOT
    );
  XLXI_3_tmp_data_3_CLKINV_31 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_tmp_data_3_CLKINV
    );
  XLXI_3_tmp_data_3_CEINV_32 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_d3,
      O => XLXI_3_tmp_data_3_CEINV
    );
  XLXI_3_tmp_data_5_DXMUX_33 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(5),
      O => XLXI_3_tmp_data_5_DXMUX
    );
  XLXI_3_tmp_data_5_DYMUX_34 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(4),
      O => XLXI_3_tmp_data_5_DYMUX
    );
  XLXI_3_tmp_data_5_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_tmp_data_5_SRINVNOT
    );
  XLXI_3_tmp_data_5_CLKINV_35 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_tmp_data_5_CLKINV
    );
  XLXI_3_tmp_data_5_CEINV_36 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_d3,
      O => XLXI_3_tmp_data_5_CEINV
    );
  XLXI_3_tmp_data_7_DXMUX_37 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(7),
      O => XLXI_3_tmp_data_7_DXMUX
    );
  XLXI_3_tmp_data_7_DYMUX_38 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_data(6),
      O => XLXI_3_tmp_data_7_DYMUX
    );
  XLXI_3_tmp_data_7_SRINV : X_INV
    port map (
      I => rst_IBUF,
      O => XLXI_3_tmp_data_7_SRINVNOT
    );
  XLXI_3_tmp_data_7_CLKINV_39 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk100m_BUFGP,
      O => XLXI_3_tmp_data_7_CLKINV
    );
  XLXI_3_tmp_data_7_CEINV_40 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_3_d3,
      O => XLXI_3_tmp_data_7_CEINV
    );
  XLXI_1_clkdiv1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => XLXI_1_clkdiv1_F,