__projnav.log

自己在ISE下用VHDL写的UART

Phase 5.8 (Checksum:9a6fa4) REAL time: 9 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 9 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 9 secs 

Writing design to file send.ncd.

Total REAL time to Placer completion: 10 secs 
Total CPU time to Placer completion: 8 secs 


Phase 1: 140 unrouted;       REAL time: 10 secs 

Phase 2: 123 unrouted;       REAL time: 16 secs 

Phase 3: 22 unrouted;       REAL time: 16 secs 

Phase 4: 0 unrouted;       REAL time: 16 secs 

Total REAL time to Router completion: 16 secs 
Total CPU time to Router completion: 15 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |BUFGCTRL_X| No   |    6 |  0.481     |  1.913      |
+-------------------------+----------+------+------+------------+-------------+
|        load_BUFGP       |BUFGCTRL_X| No   |    9 |  0.582     |  2.057      |
+-------------------------+----------+------+------+------------+-------------+
|            clkdiv       |   Local  |      |    9 |  1.958     |  3.455      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 17 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  126 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file send.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Wed Apr 12 14:58:34 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module send . . .
PAR command line: par -w -intstyle ise -ol std -t 1 send_map.ncd send.ncd send.pcf
PAR completed successfully



Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".




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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\sk\iseobject\ex/_ngo -uc
E:/sk/iseobject/ex/sk/u.ucf -p xc4vlx25-sf363-10 new_top.ngc new_top.ngd 

Reading NGO file "e:/sk/iseobject/ex/new_top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "E:/sk/iseobject/ex/sk/u.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 55340 kilobytes

Writing NGD file "new_top.ngd" ...

Writing NGDBUILD log file "new_top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "4vlx25sf363-10".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:          77 out of  21,504    1%
  Number of 4 input LUTs:              58 out of  21,504    1%
Logic Distribution:
  Number of occupied Slices:                           63 out of  10,752    1%
    Number of Slices containing only related logic:      63 out of      63  100%
    Number of Slices containing unrelated logic:          0 out of      63    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             68 out of  21,504    1%
  Number used as logic:                 58
  Number used as a route-thru:          10
  Number of bonded IOBs:                5 out of     240    2%
  Number of BUFG/BUFGCTRLs:             3 out of      32    9%
    Number used as BUFGs:                3
    Number used as BUFGCTRLs:            0

Total equivalent gate count for design:  1,088
Additional JTAG gate count for IOBs:  240
Peak Memory Usage:  123 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "new_top_map.mrp" for details.
Completed process "Map".

Mapping Module new_top . . .
MAP command line:
map -intstyle ise -p xc4vlx25-sf363-10 -cm area -pr b -k 4 -c 100 -tx off -o new_top_map.ncd new_top.ngd new_top.pcf
Mapping Module new_top: DONE



Started process "Place & Route".





Constraints file: new_top.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "new_top_map.ncd".
   "new_top" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10
Loading device for application Par from file '4vlx25.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.46 2004-07-09.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs             5 out of 240     2%
      Number of LOCed External IOBs    4 out of 5      80%

   Number of OLOGICs                   2 out of 448     1%
   Number of Slices                   63 out of 10752   1%

   Number of BUFGs                     3 out of 32      9%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897ba) REAL time: 8 secs 

......
WARNING:Place - A clock IOB  clock component is not placed at an optimal clock
   IOB site  The clock IOB component <rxd> is placed at site E7. The clock IO
   site can use the fast path between the IO and the Clock buffer/GCLK if the
   IOB is placed in the master Clock IOB Site. You may want to analyze why this
   problem exists and correct it. This is not an error so processing will
   continue.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 9 secs 

Phase 5.8
..
Phase 5.8 (Checksum:99858f) REAL time: 9 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 10 secs 

Writing design to file new_top.ncd.

Total REAL time to Placer completion: 10 secs 
Total CPU time to Placer completion: 9 secs 


Phase 1: 365 unrouted;       REAL time: 11 secs 

Phase 2: 328 unrouted;       REAL time: 19 secs 

Phase 3: 78 unrouted;       REAL time: 19 secs 

Phase 4: 0 unrouted;       REAL time: 19 secs 

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 17 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         rxd_BUFGP       |BUFGCTRL_X| No   |   10 |  0.000     |  1.894      |
+-------------------------+----------+------+------+------------+-------------+
|     clk100m_BUFGP       |BUFGCTRL_X| No   |   20 |  0.511     |  1.940      |
+-------------------------+----------+------+------+------------+-------------+
|     XLXI_1_clkdiv       |BUFGCTRL_X| No   |   15 |  0.485     |  1.890      |
+-------------------------+----------+------+------+------------+-------------+
|     XLXI_2_clkdiv       |   Local  |      |    9 |  1.024     |  1.865      |
+-------------------------+----------+------+------+------------+-------------+
|         XLXI_3_t3       |   Local  |      |    5 |  0.284     |  0.940      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 21 secs 
Total CPU time to PAR completion: 18 secs 

Peak Memory Usage:  126 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file new_top.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Wed Apr 12 15:33:44 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module new_top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 new_top_map.ncd new_top.ncd new_top.pcf
PAR completed successfully



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Started process "Generate Programming File".

Completed process "Generate Programming File".



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Compiling vhdl file E:/sk/iseobject/ex/sk/send.vhd in Library work.
Entity <send> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



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Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".




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