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the Evaluation CDs. To purchase an annual license for this software, please contact yourlocal Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to:eval@xilinx.com Thank You!Loading device database for application Par from file "new_top_map.ncd". "new_top" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10Loading device for application Par from file '4vlx25.nph' in environmentD:/Xilinx.Device speed data version: PREVIEW 1.46 2004-07-09.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 5 out of 240 2% Number of LOCed External IOBs 0 out of 5 0% Number of OLOGICs 2 out of 448 1% Number of Slices 63 out of 10752 1% Number of BUFGs 3 out of 32 9%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9897ba) REAL time: 8 secs .Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 9 secs Phase 5.8.Phase 5.8 (Checksum:9a4da8) REAL time: 10 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 10 secs Phase 9.27Phase 9.27 (Checksum:55d4a77) REAL time: 10 secs Writing design to file new_top.ncd.Total REAL time to Placer completion: 10 secs Total CPU time to Placer completion: 9 secs Phase 1: 365 unrouted; REAL time: 11 secs Phase 2: 328 unrouted; REAL time: 18 secs Phase 3: 83 unrouted; REAL time: 18 secs Phase 4: 0 unrouted; REAL time: 19 secs Total REAL time to Router completion: 19 secs Total CPU time to Router completion: 17 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+| rxd_BUFGP |BUFGCTRL_X| No | 10 | 0.000 | 1.873 |+-------------------------+----------+------+------+------------+-------------+| clk100m_BUFGP |BUFGCTRL_X| No | 20 | 0.532 | 1.941 |+-------------------------+----------+------+------+------------+-------------+| XLXI_1_clkdiv |BUFGCTRL_X| No | 15 | 0.502 | 1.927 |+-------------------------+----------+------+------+------------+-------------+| XLXI_2_clkdiv | Local | | 9 | 1.553 | 2.214 |+-------------------------+----------+------+------+------------+-------------+| XLXI_3_t3 | Local | | 5 | 1.003 | 2.288 |+-------------------------+----------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 20 secs Total CPU time to PAR completion: 18 secs Peak Memory Usage: 127 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file new_top.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Wed Apr 12 14:51:11 2006--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module new_top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 new_top_map.ncd new_top.ncd new_top.pcf
PAR completed successfully
Started process "Generate Post-Place & Route Simulation Model".Completed process "Generate Post-Place & Route Simulation Model".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 36 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file E:/sk/iseobject/ex/sk/receive.vhd in Library work.Architecture behavioral of Entity receive is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <receive> (Architecture <behavioral>).Entity <receive> analyzed. Unit <receive> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <receive>. Related source file is E:/sk/iseobject/ex/sk/receive.vhd.WARNING:Xst:653 - Signal <f4> is used but never assigned. Tied to value 0.WARNING:Xst:653 - Signal <f5> is used but never assigned. Tied to value 0.WARNING:Xst:646 - Signal <f6> is assigned but never used. Found finite state machine <FSM_0> for signal <c>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 10 | | Inputs | 0 | | Outputs | 10 | | Clock | clkdiv (rising_edge) | | Clock enable | f3 (positive) | | Power Up State | 0000000001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal <data>. Found 1-bit register for signal <do>. Found 1-bit register for signal <clkdiv>. Found 10-bit up counter for signal <count>. Found 1-bit register for signal <f1>. Found 1-bit register for signal <f2>. Found 1-bit xor2 for signal <f3>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 12 D-type flip-flop(s).Unit <receive> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...MAC inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...DSP optimizations ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <c> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Counters : 1 10-bit up counter : 1# Registers : 22 1-bit register : 22# Xors : 1 1-bit xor2 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <receive> ...Loading device for application Xst from file '4vlx25.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block receive, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10 Number of Slices: 28 out of 10752 0% Number of Slice Flip Flops: 32 out of 21504 0% Number of 4 input LUTs: 50 out of 21504 0% Number of bonded IOBs: 9 out of 242 3% Number of GCLKs: 3 out of 32 9% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clkdiv:Q | BUFG | 20 |RXD | BUFGP | 1 |clk | BUFGP | 11 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -10 Minimum period: 4.430ns (Maximum Frequency: 225.749MHz) Minimum input arrival time before clock: 2.684ns Maximum output required time after clock: 4.015ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\sk\iseobject\ex/_ngo -i -pxc4vlx25-sf363-10 receive.ngc receive.ngd Reading NGO file "e:/sk/iseobject/ex/receive.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 54316 kilobytesWriting NGD file "receive.ngd" ...Writing NGDBUILD log file "receive.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "4vlx25sf363-10".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 2Logic Utilization: Number of Slice Flip Flops: 32 out of 21,504 1% Number of 4 input LUTs: 39 out of 21,504 1%Logic Distribution: Number of occupied Slices: 31 out of 10,752 1% Number of Slices containing only related logic: 31 out of 31 100% Number of Slices containing unrelated logic: 0 out of 31 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 44 out of 21,504 1% Number used as logic: 39 Number used as a route-thru: 5 Number of bonded IOBs: 11 out of 240 4% Number of BUFG/BUFGCTRLs: 3 out of 32 9% Number used as BUFGs: 3 Number used as BUFGCTRLs: 0Total equivalent gate count for design: 544Additional JTAG gate count for IOBs: 528Peak Memory Usage: 123 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "receive_map.mrp" for details.Completed process "Map".Mapping Module receive . . .
MAP command line:
map -intstyle ise -p xc4vlx25-sf363-10 -cm area -pr b -k 4 -c 100 -tx off -o receive_map.ncd receive.ngd receive.pcf
Mapping Module receive: DONE
Started process "Place & Route".Constraints file: receive.pcfWARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36 days, this program will not operate. For more information about thisproduct, please refer to the Evaluation Agreement, which was shipped toyou along with the Evaluation CDs. To purchase an annual license for this software, please contact yourlocal Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to:eval@xilinx.com Thank You!Loading device database for application Par from file "receive_map.ncd". "receive" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10Loading device for application Par from file '4vlx25.nph' in environmentD:/Xilinx.Device speed data version: PREVIEW 1.46 2004-07-09.Resolving physical constraints.Finished resolving physical constraints.⌨️ 快捷键说明
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