receive_timesim.vhd

自己在ISE下用VHDL写的UART

      ADR1 => c_FFd6,
      ADR2 => c_FFd5,
      ADR3 => c_FFd4,
      O => data_2_G
    );
  Q_n001913 : X_LUT4
    generic map(
      INIT => X"EEEA"
    )
    port map (
      ADR0 => CHOICE633,
      ADR1 => data_2,
      ADR2 => CHOICE635,
      ADR3 => N1292,
      O => Q_n001913_O
    );
  data_2_126 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_2_DXMUX,
      CE => data_2_CEINV,
      CLK => data_2_CLKINV,
      SET => GND,
      RST => data_2_FFX_RST,
      O => data_2
    );
  data_2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_2_FFX_RST
    );
  c_FFd9_127 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd10_DYMUX,
      CE => c_FFd10_CEINV,
      CLK => c_FFd10_CLKINV,
      SET => GND,
      RST => c_FFd10_FFY_RST,
      O => c_FFd9
    );
  c_FFd10_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd10_FFY_RST
    );
  c_FFd10_128 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => c_FFd10_DXMUX,
      CE => c_FFd10_CEINV,
      CLK => c_FFd10_CLKINV,
      SET => c_FFd10_FFX_SET,
      RST => GND,
      O => c_FFd10
    );
  c_FFd10_FFX_SETOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd10_FFX_SET
    );
  f1_129 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => f1_DYMUX,
      CE => f1_CEINV,
      CLK => f1_CLKINVNOT,
      SET => GND,
      RST => f1_FFY_RST,
      O => f1
    );
  f1_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => f1_FFY_RST
    );
  Q_n00210 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c_FFd5,
      ADR2 => VCC,
      ADR3 => RXD_BUFGP,
      O => CHOICE621_G
    );
  Q_n00243 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => c_FFd3,
      ADR1 => c_FFd9,
      ADR2 => VCC,
      ADR3 => c_FFd1,
      O => data_7_G
    );
  Q_n002313 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => data_6,
      ADR1 => N1287,
      ADR2 => CHOICE623,
      ADR3 => CHOICE621,
      O => Q_n002313_O
    );
  data_6_130 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_6_DXMUX,
      CE => data_6_CEINV,
      CLK => data_6_CLKINV,
      SET => GND,
      RST => data_6_FFX_RST,
      O => data_6
    );
  data_6_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_6_FFX_RST
    );
  Q_n002413 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => CHOICE605,
      ADR1 => data_7,
      ADR2 => N1287,
      ADR3 => CHOICE603,
      O => Q_n002413_O
    );
  data_7_131 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_7_DXMUX,
      CE => data_7_CEINV,
      CLK => data_7_CLKINV,
      SET => GND,
      RST => data_7_FFX_RST,
      O => data_7
    );
  data_7_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_7_FFX_RST
    );
  count_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DYMUX,
      CE => count_0_CEINV,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_0_SRINV,
      O => count(1)
    );
  count_LPM_COUNTER_1_n0000_0_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => count(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_N728
    );
  count_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_0_DXMUX,
      CE => count_0_CEINV,
      CLK => count_0_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_0_SRINV,
      O => count(0)
    );
  Q_n0016_SW10 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => c_FFd9,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => RXD_BUFGP,
      O => CHOICE594_F
    );
  c_FFd1_132 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd2_DYMUX,
      CE => c_FFd2_CEINV,
      CLK => c_FFd2_CLKINV,
      SET => GND,
      RST => c_FFd2_FFY_RST,
      O => c_FFd1
    );
  c_FFd2_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd2_FFY_RST
    );
  c_FFd2_133 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd2_DXMUX,
      CE => c_FFd2_CEINV,
      CLK => c_FFd2_CLKINV,
      SET => GND,
      RST => c_FFd2_FFX_RST,
      O => c_FFd2
    );
  c_FFd2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd2_FFX_RST
    );
  c_FFd3_134 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd4_DYMUX,
      CE => c_FFd4_CEINV,
      CLK => c_FFd4_CLKINV,
      SET => GND,
      RST => c_FFd4_FFY_RST,
      O => c_FFd3
    );
  c_FFd4_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd4_FFY_RST
    );
  c_FFd4_135 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd4_DXMUX,
      CE => c_FFd4_CEINV,
      CLK => c_FFd4_CLKINV,
      SET => GND,
      RST => c_FFd4_FFX_RST,
      O => c_FFd4
    );
  c_FFd4_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd4_FFX_RST
    );
  c_FFd5_136 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd6_DYMUX,
      CE => c_FFd6_CEINV,
      CLK => c_FFd6_CLKINV,
      SET => GND,
      RST => c_FFd6_FFY_RST,
      O => c_FFd5
    );
  c_FFd6_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd6_FFY_RST
    );
  c_FFd6_137 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd6_DXMUX,
      CE => c_FFd6_CEINV,
      CLK => c_FFd6_CLKINV,
      SET => GND,
      RST => c_FFd6_FFX_RST,
      O => c_FFd6
    );
  c_FFd6_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd6_FFX_RST
    );
  Q_n001311 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => count(7),
      ADR3 => count(6),
      O => CHOICE656_F
    );
  Q_n00230 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => c_FFd3,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => RXD_BUFGP,
      O => CHOICE621_F
    );
  Q_n00203 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => c_FFd5,
      ADR1 => VCC,
      ADR2 => c_FFd7,
      ADR3 => c_FFd4,
      O => data_3_G
    );
  Q_n002013 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE627,
      ADR1 => N1292,
      ADR2 => CHOICE629,
      ADR3 => data_3,
      O => Q_n002013_O
    );
  data_3_138 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_3_DXMUX,
      CE => data_3_CEINV,
      CLK => data_3_CLKINV,
      SET => GND,
      RST => data_3_FFX_RST,
      O => data_3
    );
  data_3_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_3_FFX_RST
    );
  Q_n00220 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => RXD_BUFGP,
      ADR2 => c_FFd4,
      ADR3 => VCC,
      O => CHOICE615_F
    );
  Q_n00213 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c_FFd6,
      ADR2 => c_FFd4,
      ADR3 => c_FFd7,
      O => data_4_G
    );
  Q_n002113 : X_LUT4
    generic map(
      INIT => X"FAEA"
    )
    port map (
      ADR0 => CHOICE609,
      ADR1 => N1292,
      ADR2 => data_4,
      ADR3 => CHOICE611,
      O => Q_n002113_O
    );
  Q_n00223 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => c_FFd7,
      ADR1 => VCC,
      ADR2 => c_FFd5,
      ADR3 => c_FFd6,
      O => data_5_G
    );
  data_4_139 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_4_DXMUX,
      CE => data_4_CEINV,
      CLK => data_4_CLKINV,
      SET => GND,
      RST => data_4_FFX_RST,
      O => data_4
    );
  data_4_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_4_FFX_RST
    );
  Q_n002213 : X_LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      ADR0 => data_5,
      ADR1 => N1292,
      ADR2 => CHOICE615,
      ADR3 => CHOICE617,
      O => Q_n002213_O
    );
  Q_n00233 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => c_FFd1,
      ADR1 => VCC,
      ADR2 => c_FFd2,
      ADR3 => c_FFd9,
      O => data_6_G
    );
  data_5_140 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_5_DXMUX,
      CE => data_5_CEINV,
      CLK => data_5_CLKINV,
      SET => GND,
      RST => data_5_FFX_RST,
      O => data_5
    );
  data_5_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_5_FFX_RST
    );
  count_3 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_2_DYMUX,
      CE => count_2_CEINV,
      CLK => count_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_2_SRINV,
      O => count(3)
    );
  count_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_2_DXMUX,
      CE => count_2_CEINV,
      CLK => count_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_2_SRINV,
      O => count(2)
    );
  count_5 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_4_DYMUX,
      CE => count_4_CEINV,
      CLK => count_4_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_4_SRINV,
      O => count(5)
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  clk_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk_BUFGP_IBUFG,
      O => clk_BUFGP
    );
  clkdiv_BUFG_BUF : X_CKBUF
    port map (
      I => clkdiv1,
      O => clkdiv
    );
  RXD_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => RXD_BUFGP_IBUFG,
      O => RXD_BUFGP
    );
  PWR_GND_0_LOGICAL_ZERO : X_ZERO
    port map (
      O => PWR_GND_0_GND
    );
  PWR_GND_0_LOGICAL_ONE : X_ONE
    port map (
      O => PWR_GND_0_VCC
    );
  count_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_0_G
    );
  count_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => count(2),
      O => count_2_F
    );
  count_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => count(3),
      ADR3 => VCC,
      O => count_2_G
    );
  count_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => count(4),
      O => count_4_F
    );
  count_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => count(5),
      ADR3 => VCC,
      O => count_4_G
    );
  count_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_6_F
    );
  count_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_6_G
    );
  count_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_8_F
    );
  NlwBlock_receive_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_receive_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;