receive_timesim.vhd

自己在ISE下用VHDL写的UART

      O => count_LPM_COUNTER_1_n0000_4_cyo
    );
  count_4_CYMUXF2_83 : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_LOGIC_ZERO,
      SEL => count_4_F,
      O => count_4_CYMUXF2
    );
  count_4_CYINIT_84 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_3_cyo,
      O => count_4_CYINIT
    );
  count_4_DYMUX_85 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_XORG,
      O => count_4_DYMUX
    );
  count_4_XORG_86 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_4_cyo,
      I1 => count_4_G,
      O => count_4_XORG
    );
  count_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_5_cyo
    );
  count_4_FASTCARRY_87 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_3_cyo,
      O => count_4_FASTCARRY
    );
  count_4_CYAND_88 : X_AND2
    port map (
      I0 => count_4_G,
      I1 => count_4_F,
      O => count_4_CYAND
    );
  count_4_CYMUXFAST_89 : X_MUX2
    port map (
      IA => count_4_CYMUXG2,
      IB => count_4_FASTCARRY,
      SEL => count_4_CYAND,
      O => count_4_CYMUXFAST
    );
  count_4_CYMUXG2_90 : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_CYMUXF2,
      SEL => count_4_G,
      O => count_4_CYMUXG2
    );
  count_4_SRINV_91 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015,
      O => count_4_SRINV
    );
  count_4_CLKINV_92 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_4_CLKINV
    );
  count_4_CEINV_93 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => count_4_CEINV
    );
  count_6_LOGIC_ZERO_94 : X_ZERO
    port map (
      O => count_6_LOGIC_ZERO
    );
  count_6_DXMUX_95 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_XORF,
      O => count_6_DXMUX
    );
  count_6_XORF_96 : X_XOR2
    port map (
      I0 => count_6_CYINIT,
      I1 => count_6_F,
      O => count_6_XORF
    );
  count_6_CYMUXF : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_CYINIT,
      SEL => count_6_F,
      O => count_LPM_COUNTER_1_n0000_6_cyo
    );
  count_6_CYMUXF2_97 : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_LOGIC_ZERO,
      SEL => count_6_F,
      O => count_6_CYMUXF2
    );
  count_6_CYINIT_98 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_5_cyo,
      O => count_6_CYINIT
    );
  count_6_DYMUX_99 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_XORG,
      O => count_6_DYMUX
    );
  count_6_XORG_100 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_6_cyo,
      I1 => count_6_G,
      O => count_6_XORG
    );
  count_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_6_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_7_cyo
    );
  count_6_FASTCARRY_101 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_5_cyo,
      O => count_6_FASTCARRY
    );
  count_6_CYAND_102 : X_AND2
    port map (
      I0 => count_6_G,
      I1 => count_6_F,
      O => count_6_CYAND
    );
  count_6_CYMUXFAST_103 : X_MUX2
    port map (
      IA => count_6_CYMUXG2,
      IB => count_6_FASTCARRY,
      SEL => count_6_CYAND,
      O => count_6_CYMUXFAST
    );
  count_6_CYMUXG2_104 : X_MUX2
    port map (
      IA => count_6_LOGIC_ZERO,
      IB => count_6_CYMUXF2,
      SEL => count_6_G,
      O => count_6_CYMUXG2
    );
  count_6_SRINV_105 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015,
      O => count_6_SRINV
    );
  count_6_CLKINV_106 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_6_CLKINV
    );
  count_6_CEINV_107 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => count_6_CEINV
    );
  count_8_LOGIC_ZERO_108 : X_ZERO
    port map (
      O => count_8_LOGIC_ZERO
    );
  count_8_DXMUX_109 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_8_XORF,
      O => count_8_DXMUX
    );
  count_8_XORF_110 : X_XOR2
    port map (
      I0 => count_8_CYINIT,
      I1 => count_8_F,
      O => count_8_XORF
    );
  count_8_CYMUXF : X_MUX2
    port map (
      IA => count_8_LOGIC_ZERO,
      IB => count_8_CYINIT,
      SEL => count_8_F,
      O => count_LPM_COUNTER_1_n0000_8_cyo
    );
  count_8_CYINIT_111 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_7_cyo,
      O => count_8_CYINIT
    );
  count_8_DYMUX_112 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_8_XORG,
      O => count_8_DYMUX
    );
  count_8_XORG_113 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_8_cyo,
      I1 => count_9_rt,
      O => count_8_XORG
    );
  count_8_SRINV_114 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015,
      O => count_8_SRINV
    );
  count_8_CLKINV_115 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_8_CLKINV
    );
  count_8_CEINV_116 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => count_8_CEINV
    );
  do_OBUF_117 : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => do_OBUF,
      CTL => do_ENABLE,
      O => do
    );
  do_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => do_ENABLE
    );
  data_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_0,
      CTL => data_0_ENABLE,
      O => data(0)
    );
  data_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_0_ENABLE
    );
  Ker1290_SW0 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => c_FFd3,
      ADR1 => VCC,
      ADR2 => c_FFd2,
      ADR3 => c_FFd1,
      O => N1292_G
    );
  Q_n00171 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => N1266,
      ADR1 => RXD_BUFGP,
      ADR2 => do_OBUF,
      ADR3 => c_FFd1,
      O => Q_n00171_O
    );
  Ker1290 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd8,
      ADR1 => c_FFd9,
      ADR2 => Ker1290_SW0_O,
      ADR3 => c_FFd10,
      O => N1292_F
    );
  do_118 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => do_OBUF_DYMUX,
      CE => VCC,
      CLK => do_OBUF_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => do_OBUF_SRINV,
      O => do_OBUF
    );
  Q_n00180 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => c_FFd8,
      ADR1 => RXD_BUFGP,
      ADR2 => VCC,
      ADR3 => VCC,
      O => do_OBUF_F
    );
  Q_n001332 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => count(6),
      ADR1 => count(7),
      ADR2 => CHOICE654,
      ADR3 => CHOICE661,
      O => Q_n0013_F
    );
  f1_N951 : X_LUT4
    generic map(
      INIT => X"F00F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => f2,
      ADR3 => f1,
      O => clkdiv1_G
    );
  clkdiv_119 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => clkdiv1_DYMUX,
      CE => clkdiv1_CEINV,
      CLK => clkdiv1_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => clkdiv1_SRINV,
      O => clkdiv1
    );
  Mxor_f3_Result1 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => f2,
      ADR3 => f1,
      O => clkdiv1_F
    );
  data_0_120 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => f2_DYMUX,
      CE => f2_CEINV,
      CLK => f2_CLKINV,
      SET => GND,
      RST => f2_FFY_RST,
      O => data_0
    );
  f2_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => f2_FFY_RST
    );
  Q_n00251 : X_LUT4
    generic map(
      INIT => X"EFE0"
    )
    port map (
      ADR0 => c_FFd9,
      ADR1 => N1266,
      ADR2 => f2,
      ADR3 => c_FFd1,
      O => Q_n00251_O
    );
  f2_121 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => f2_DXMUX,
      CE => f2_CEINV,
      CLK => f2_CLKINV,
      SET => GND,
      RST => f2_FFX_RST,
      O => f2
    );
  f2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => f2_FFX_RST
    );
  Q_n001812 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd4,
      ADR1 => c_FFd5,
      ADR2 => c_FFd6,
      ADR3 => CHOICE643,
      O => data_1_G
    );
  Q_n001833 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => data_1,
      ADR1 => CHOICE642,
      ADR2 => Q_n001812_O,
      ADR3 => CHOICE639,
      O => Q_n001833_O
    );
  Ker12641 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => c_FFd3,
      ADR1 => VCC,
      ADR2 => c_FFd2,
      ADR3 => N1287,
      O => N1266_F
    );
  data_1_122 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => data_1_DXMUX,
      CE => data_1_CEINV,
      CLK => data_1_CLKINV,
      SET => GND,
      RST => data_1_FFX_RST,
      O => data_1
    );
  data_1_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => data_1_FFX_RST
    );
  Q_n00151 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => CHOICE661,
      ADR1 => CHOICE656,
      ADR2 => CHOICE654,
      ADR3 => f3,
      O => Q_n0015_F
    );
  Q_n00185 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd1,
      ADR1 => c_FFd2,
      ADR2 => c_FFd10,
      ADR3 => c_FFd3,
      O => CHOICE603_G
    );
  Q_n00200 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c_FFd6,
      ADR2 => RXD_BUFGP,
      ADR3 => VCC,
      O => CHOICE627_F
    );
  Q_n00186 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => c_FFd9,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => c_FFd7,
      O => CHOICE594_G
    );
  Q_n00240 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c_FFd2,
      ADR2 => VCC,
      ADR3 => RXD_BUFGP,
      O => CHOICE603_F
    );
  count_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_4_DXMUX,
      CE => count_4_CEINV,
      CLK => count_4_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_4_SRINV,
      O => count(4)
    );
  count_7 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_6_DYMUX,
      CE => count_6_CEINV,
      CLK => count_6_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_6_SRINV,
      O => count(7)
    );
  count_6 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_6_DXMUX,
      CE => count_6_CEINV,
      CLK => count_6_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_6_SRINV,
      O => count(6)
    );
  count_9_rt_123 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => count(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => count_9_rt
    );
  count_9 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_8_DYMUX,
      CE => count_8_CEINV,
      CLK => count_8_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_8_SRINV,
      O => count(9)
    );
  count_8 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => count_8_DXMUX,
      CE => count_8_CEINV,
      CLK => count_8_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => count_8_SRINV,
      O => count(8)
    );
  c_FFd7_124 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd8_DYMUX,
      CE => c_FFd8_CEINV,
      CLK => c_FFd8_CLKINV,
      SET => GND,
      RST => c_FFd8_FFY_RST,
      O => c_FFd7
    );
  c_FFd8_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd8_FFY_RST
    );
  c_FFd8_125 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c_FFd8_DXMUX,
      CE => c_FFd8_CEINV,
      CLK => c_FFd8_CLKINV,
      SET => GND,
      RST => c_FFd8_FFX_RST,
      O => c_FFd8
    );
  c_FFd8_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GSR,
      O => c_FFd8_FFX_RST
    );
  Ker1285_SW0 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,