receive_timesim.vhd

自己在ISE下用VHDL写的UART

    )
    port map (
      I => Q_n0015_G,
      O => CHOICE654
    );
  Q_n00190 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c_FFd7,
      ADR2 => RXD_BUFGP,
      ADR3 => VCC,
      O => CHOICE627_G
    );
  CHOICE627_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE627_F,
      O => CHOICE627
    );
  CHOICE627_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE627_G,
      O => CHOICE633
    );
  CHOICE603_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE603_F,
      O => CHOICE603
    );
  CHOICE603_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE603_G,
      O => CHOICE642
    );
  CHOICE594_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE594_F,
      O => CHOICE594
    );
  CHOICE594_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE594_G,
      O => CHOICE643
    );
  c_FFd2_DXMUX_16 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd3,
      O => c_FFd2_DXMUX
    );
  c_FFd2_DYMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd2,
      O => c_FFd2_DYMUX
    );
  c_FFd2_CLKINV_18 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd2_CLKINV
    );
  c_FFd2_CEINV_19 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => c_FFd2_CEINV
    );
  c_FFd4_DXMUX_20 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd5,
      O => c_FFd4_DXMUX
    );
  c_FFd4_DYMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd4,
      O => c_FFd4_DYMUX
    );
  c_FFd4_CLKINV_22 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd4_CLKINV
    );
  c_FFd4_CEINV_23 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => c_FFd4_CEINV
    );
  c_FFd6_DXMUX_24 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd7,
      O => c_FFd6_DXMUX
    );
  c_FFd6_DYMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd6,
      O => c_FFd6_DYMUX
    );
  c_FFd6_CLKINV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd6_CLKINV
    );
  c_FFd6_CEINV_27 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => c_FFd6_CEINV
    );
  c_FFd8_DXMUX_28 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd9,
      O => c_FFd8_DXMUX
    );
  c_FFd8_DYMUX_29 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd8,
      O => c_FFd8_DYMUX
    );
  c_FFd8_CLKINV_30 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd8_CLKINV
    );
  c_FFd8_CEINV_31 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => c_FFd8_CEINV
    );
  CHOICE656_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE656_F,
      O => CHOICE656
    );
  data_2_DXMUX_32 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001913_O,
      O => data_2_DXMUX
    );
  data_2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_2_G,
      O => CHOICE635
    );
  data_2_CLKINV_33 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_2_CLKINV
    );
  data_2_CEINV_34 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_2_CEINV
    );
  c_FFd10_DXMUX_35 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd1,
      O => c_FFd10_DXMUX
    );
  c_FFd10_DYMUX_36 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => c_FFd10,
      O => c_FFd10_DYMUX
    );
  c_FFd10_CLKINV_37 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => c_FFd10_CLKINV
    );
  c_FFd10_CEINV_38 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => c_FFd10_CEINV
    );
  f1_DYMUX_39 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f1_BYINVNOT,
      O => f1_DYMUX
    );
  f1_BYINV : X_INV
    port map (
      I => f1,
      O => f1_BYINVNOT
    );
  f1_CLKINV : X_INV
    port map (
      I => RXD_BUFGP,
      O => f1_CLKINVNOT
    );
  f1_CEINV_40 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f1_N95,
      O => f1_CEINV
    );
  CHOICE621_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE621_F,
      O => CHOICE621
    );
  CHOICE621_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE621_G,
      O => CHOICE609
    );
  data_3_DXMUX_41 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n002013_O,
      O => data_3_DXMUX
    );
  data_3_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_3_G,
      O => CHOICE629
    );
  data_3_CLKINV_42 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_3_CLKINV
    );
  data_3_CEINV_43 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_3_CEINV
    );
  CHOICE615_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => CHOICE615_F,
      O => CHOICE615
    );
  data_4_DXMUX_44 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n002113_O,
      O => data_4_DXMUX
    );
  data_4_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_4_G,
      O => CHOICE611
    );
  data_4_CLKINV_45 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_4_CLKINV
    );
  data_4_CEINV_46 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_4_CEINV
    );
  data_5_DXMUX_47 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n002213_O,
      O => data_5_DXMUX
    );
  data_5_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_5_G,
      O => CHOICE617
    );
  data_5_CLKINV_48 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_5_CLKINV
    );
  data_5_CEINV_49 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_5_CEINV
    );
  data_6_DXMUX_50 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n002313_O,
      O => data_6_DXMUX
    );
  data_6_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_6_G,
      O => CHOICE623
    );
  data_6_CLKINV_51 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_6_CLKINV
    );
  data_6_CEINV_52 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_6_CEINV
    );
  data_7_DXMUX_53 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n002413_O,
      O => data_7_DXMUX
    );
  data_7_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_7_G,
      O => CHOICE605
    );
  data_7_CLKINV_54 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_7_CLKINV
    );
  data_7_CEINV_55 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_7_CEINV
    );
  count_0_LOGIC_ZERO_56 : X_ZERO
    port map (
      O => count_0_LOGIC_ZERO
    );
  count_0_LOGIC_ONE_57 : X_ONE
    port map (
      O => count_0_LOGIC_ONE
    );
  count_0_DXMUX_58 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_N728,
      O => count_0_DXMUX
    );
  count_0_CYMUXF : X_MUX2
    port map (
      IA => count_0_LOGIC_ONE,
      IB => count_0_CYINIT,
      SEL => count_N728,
      O => count_LPM_COUNTER_1_n0000_0_cyo
    );
  count_0_CYINIT_59 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => count_0_CYINIT
    );
  count_0_DYMUX_60 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_0_XORG,
      O => count_0_DYMUX
    );
  count_0_XORG_61 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_0_cyo,
      I1 => count_0_G,
      O => count_0_XORG
    );
  count_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_0_CYMUXG,
      O => count_LPM_COUNTER_1_n0000_1_cyo
    );
  count_0_CYMUXG_62 : X_MUX2
    port map (
      IA => count_0_LOGIC_ZERO,
      IB => count_LPM_COUNTER_1_n0000_0_cyo,
      SEL => count_0_G,
      O => count_0_CYMUXG
    );
  count_0_SRINV_63 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015,
      O => count_0_SRINV
    );
  count_0_CLKINV_64 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_0_CLKINV
    );
  count_0_CEINV_65 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => count_0_CEINV
    );
  count_2_LOGIC_ZERO_66 : X_ZERO
    port map (
      O => count_2_LOGIC_ZERO
    );
  count_2_DXMUX_67 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_XORF,
      O => count_2_DXMUX
    );
  count_2_XORF_68 : X_XOR2
    port map (
      I0 => count_2_CYINIT,
      I1 => count_2_F,
      O => count_2_XORF
    );
  count_2_CYMUXF : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_CYINIT,
      SEL => count_2_F,
      O => count_LPM_COUNTER_1_n0000_2_cyo
    );
  count_2_CYMUXF2_69 : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_LOGIC_ZERO,
      SEL => count_2_F,
      O => count_2_CYMUXF2
    );
  count_2_CYINIT_70 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_1_cyo,
      O => count_2_CYINIT
    );
  count_2_DYMUX_71 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_XORG,
      O => count_2_DYMUX
    );
  count_2_XORG_72 : X_XOR2
    port map (
      I0 => count_LPM_COUNTER_1_n0000_2_cyo,
      I1 => count_2_G,
      O => count_2_XORG
    );
  count_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_2_CYMUXFAST,
      O => count_LPM_COUNTER_1_n0000_3_cyo
    );
  count_2_FASTCARRY_73 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_LPM_COUNTER_1_n0000_1_cyo,
      O => count_2_FASTCARRY
    );
  count_2_CYAND_74 : X_AND2
    port map (
      I0 => count_2_G,
      I1 => count_2_F,
      O => count_2_CYAND
    );
  count_2_CYMUXFAST_75 : X_MUX2
    port map (
      IA => count_2_CYMUXG2,
      IB => count_2_FASTCARRY,
      SEL => count_2_CYAND,
      O => count_2_CYMUXFAST
    );
  count_2_CYMUXG2_76 : X_MUX2
    port map (
      IA => count_2_LOGIC_ZERO,
      IB => count_2_CYMUXF2,
      SEL => count_2_G,
      O => count_2_CYMUXG2
    );
  count_2_SRINV_77 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015,
      O => count_2_SRINV
    );
  count_2_CLKINV_78 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_2_CLKINV
    );
  count_2_CEINV_79 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => count_2_CEINV
    );
  count_4_LOGIC_ZERO_80 : X_ZERO
    port map (
      O => count_4_LOGIC_ZERO
    );
  count_4_DXMUX_81 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => count_4_XORF,
      O => count_4_DXMUX
    );
  count_4_XORF_82 : X_XOR2
    port map (
      I0 => count_4_CYINIT,
      I1 => count_4_F,
      O => count_4_XORF
    );
  count_4_CYMUXF : X_MUX2
    port map (
      IA => count_4_LOGIC_ZERO,
      IB => count_4_CYINIT,
      SEL => count_4_F,