receive_timesim.vhd

自己在ISE下用VHDL写的UART

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 10 -pcf receive.pcf -ngm receive.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim receive.ncd receive_timesim.vhd 
-- Input file    : receive.ncd
-- Output file   : receive_timesim.vhd
-- Design name   : receive
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 4vlx25sf363-10 (PREVIEW 1.46 2004-07-09)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity receive is
  port (
    do : out STD_LOGIC; 
    RXD : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    data : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end receive;

architecture Structure of receive is
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal data_1 : STD_LOGIC; 
  signal data_2 : STD_LOGIC; 
  signal data_3 : STD_LOGIC; 
  signal data_4 : STD_LOGIC; 
  signal data_5 : STD_LOGIC; 
  signal data_6 : STD_LOGIC; 
  signal data_7 : STD_LOGIC; 
  signal RXD_BUFGP_IBUFG : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal clkdiv1 : STD_LOGIC; 
  signal clkdiv : STD_LOGIC; 
  signal RXD_BUFGP : STD_LOGIC; 
  signal c_FFd10 : STD_LOGIC; 
  signal c_FFd8 : STD_LOGIC; 
  signal c_FFd9 : STD_LOGIC; 
  signal Ker1290_SW0_O : STD_LOGIC; 
  signal c_FFd3 : STD_LOGIC; 
  signal c_FFd2 : STD_LOGIC; 
  signal c_FFd1 : STD_LOGIC; 
  signal N1292 : STD_LOGIC; 
  signal f1_N95 : STD_LOGIC; 
  signal do_OBUF : STD_LOGIC; 
  signal N1266 : STD_LOGIC; 
  signal CHOICE639 : STD_LOGIC; 
  signal Q_n0013 : STD_LOGIC; 
  signal f2 : STD_LOGIC; 
  signal f1 : STD_LOGIC; 
  signal f3 : STD_LOGIC; 
  signal CHOICE654 : STD_LOGIC; 
  signal CHOICE661 : STD_LOGIC; 
  signal CHOICE594 : STD_LOGIC; 
  signal data_0 : STD_LOGIC; 
  signal CHOICE642 : STD_LOGIC; 
  signal Q_n001812_O : STD_LOGIC; 
  signal CHOICE643 : STD_LOGIC; 
  signal c_FFd6 : STD_LOGIC; 
  signal c_FFd5 : STD_LOGIC; 
  signal c_FFd4 : STD_LOGIC; 
  signal N1287 : STD_LOGIC; 
  signal c_FFd7 : STD_LOGIC; 
  signal CHOICE635 : STD_LOGIC; 
  signal CHOICE656 : STD_LOGIC; 
  signal Q_n0015 : STD_LOGIC; 
  signal CHOICE627 : STD_LOGIC; 
  signal CHOICE633 : STD_LOGIC; 
  signal CHOICE603 : STD_LOGIC; 
  signal CHOICE621 : STD_LOGIC; 
  signal CHOICE609 : STD_LOGIC; 
  signal CHOICE629 : STD_LOGIC; 
  signal CHOICE615 : STD_LOGIC; 
  signal CHOICE611 : STD_LOGIC; 
  signal CHOICE617 : STD_LOGIC; 
  signal CHOICE623 : STD_LOGIC; 
  signal CHOICE605 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal clk_INBUF_B : STD_LOGIC; 
  signal clk_ENABLE : STD_LOGIC; 
  signal data_1_ENABLE : STD_LOGIC; 
  signal data_2_ENABLE : STD_LOGIC; 
  signal data_3_ENABLE : STD_LOGIC; 
  signal data_4_ENABLE : STD_LOGIC; 
  signal data_5_ENABLE : STD_LOGIC; 
  signal data_6_ENABLE : STD_LOGIC; 
  signal data_7_ENABLE : STD_LOGIC; 
  signal RXD_INBUF_B : STD_LOGIC; 
  signal RXD_ENABLE : STD_LOGIC; 
  signal N1292_F : STD_LOGIC; 
  signal N1292_G : STD_LOGIC; 
  signal do_OBUF_F : STD_LOGIC; 
  signal do_OBUF_DYMUX : STD_LOGIC; 
  signal Q_n00171_O : STD_LOGIC; 
  signal do_OBUF_SRINV : STD_LOGIC; 
  signal do_OBUF_CLKINV : STD_LOGIC; 
  signal clkdiv1_F : STD_LOGIC; 
  signal clkdiv1_DYMUX : STD_LOGIC; 
  signal clkdiv1_G : STD_LOGIC; 
  signal clkdiv1_BYINVNOT : STD_LOGIC; 
  signal clkdiv1_SRINV : STD_LOGIC; 
  signal clkdiv1_CLKINV : STD_LOGIC; 
  signal clkdiv1_CEINV : STD_LOGIC; 
  signal Q_n0013_F : STD_LOGIC; 
  signal Q_n0013_G : STD_LOGIC; 
  signal f2_DXMUX : STD_LOGIC; 
  signal Q_n00251_O : STD_LOGIC; 
  signal f2_DYMUX : STD_LOGIC; 
  signal Q_n0016_SW16_O : STD_LOGIC; 
  signal f2_CLKINV : STD_LOGIC; 
  signal f2_CEINV : STD_LOGIC; 
  signal data_1_DXMUX : STD_LOGIC; 
  signal Q_n001833_O : STD_LOGIC; 
  signal data_1_G : STD_LOGIC; 
  signal data_1_CLKINV : STD_LOGIC; 
  signal data_1_CEINV : STD_LOGIC; 
  signal N1266_F : STD_LOGIC; 
  signal N1266_G : STD_LOGIC; 
  signal Q_n0015_F : STD_LOGIC; 
  signal Q_n0015_G : STD_LOGIC; 
  signal CHOICE627_F : STD_LOGIC; 
  signal CHOICE627_G : STD_LOGIC; 
  signal CHOICE603_F : STD_LOGIC; 
  signal CHOICE603_G : STD_LOGIC; 
  signal CHOICE594_F : STD_LOGIC; 
  signal CHOICE594_G : STD_LOGIC; 
  signal c_FFd2_DXMUX : STD_LOGIC; 
  signal c_FFd2_DYMUX : STD_LOGIC; 
  signal c_FFd2_CLKINV : STD_LOGIC; 
  signal c_FFd2_CEINV : STD_LOGIC; 
  signal c_FFd4_DXMUX : STD_LOGIC; 
  signal c_FFd4_DYMUX : STD_LOGIC; 
  signal c_FFd4_CLKINV : STD_LOGIC; 
  signal c_FFd4_CEINV : STD_LOGIC; 
  signal c_FFd6_DXMUX : STD_LOGIC; 
  signal c_FFd6_DYMUX : STD_LOGIC; 
  signal c_FFd6_CLKINV : STD_LOGIC; 
  signal c_FFd6_CEINV : STD_LOGIC; 
  signal c_FFd8_DXMUX : STD_LOGIC; 
  signal c_FFd8_DYMUX : STD_LOGIC; 
  signal c_FFd8_CLKINV : STD_LOGIC; 
  signal c_FFd8_CEINV : STD_LOGIC; 
  signal CHOICE656_F : STD_LOGIC; 
  signal data_2_DXMUX : STD_LOGIC; 
  signal Q_n001913_O : STD_LOGIC; 
  signal data_2_G : STD_LOGIC; 
  signal data_2_CLKINV : STD_LOGIC; 
  signal data_2_CEINV : STD_LOGIC; 
  signal c_FFd10_DXMUX : STD_LOGIC; 
  signal c_FFd10_DYMUX : STD_LOGIC; 
  signal c_FFd10_CLKINV : STD_LOGIC; 
  signal c_FFd10_CEINV : STD_LOGIC; 
  signal f1_DYMUX : STD_LOGIC; 
  signal f1_BYINVNOT : STD_LOGIC; 
  signal f1_CLKINVNOT : STD_LOGIC; 
  signal f1_CEINV : STD_LOGIC; 
  signal CHOICE621_F : STD_LOGIC; 
  signal CHOICE621_G : STD_LOGIC; 
  signal data_3_DXMUX : STD_LOGIC; 
  signal Q_n002013_O : STD_LOGIC; 
  signal data_3_G : STD_LOGIC; 
  signal data_3_CLKINV : STD_LOGIC; 
  signal data_3_CEINV : STD_LOGIC; 
  signal CHOICE615_F : STD_LOGIC; 
  signal data_4_DXMUX : STD_LOGIC; 
  signal Q_n002113_O : STD_LOGIC; 
  signal data_4_G : STD_LOGIC; 
  signal data_4_CLKINV : STD_LOGIC; 
  signal data_4_CEINV : STD_LOGIC; 
  signal data_5_DXMUX : STD_LOGIC; 
  signal Q_n002213_O : STD_LOGIC; 
  signal data_5_G : STD_LOGIC; 
  signal data_5_CLKINV : STD_LOGIC; 
  signal data_5_CEINV : STD_LOGIC; 
  signal data_6_DXMUX : STD_LOGIC; 
  signal Q_n002313_O : STD_LOGIC; 
  signal data_6_G : STD_LOGIC; 
  signal data_6_CLKINV : STD_LOGIC; 
  signal data_6_CEINV : STD_LOGIC; 
  signal data_7_DXMUX : STD_LOGIC; 
  signal Q_n002413_O : STD_LOGIC; 
  signal data_7_G : STD_LOGIC; 
  signal data_7_CLKINV : STD_LOGIC; 
  signal data_7_CEINV : STD_LOGIC; 
  signal count_0_DXMUX : STD_LOGIC; 
  signal count_0_LOGIC_ONE : STD_LOGIC; 
  signal count_0_CYINIT : STD_LOGIC; 
  signal count_N728 : STD_LOGIC; 
  signal count_0_DYMUX : STD_LOGIC; 
  signal count_0_XORG : STD_LOGIC; 
  signal count_0_CYMUXG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal count_0_LOGIC_ZERO : STD_LOGIC; 
  signal count_0_G : STD_LOGIC; 
  signal count_0_SRINV : STD_LOGIC; 
  signal count_0_CLKINV : STD_LOGIC; 
  signal count_0_CEINV : STD_LOGIC; 
  signal count_2_DXMUX : STD_LOGIC; 
  signal count_2_XORF : STD_LOGIC; 
  signal count_2_CYINIT : STD_LOGIC; 
  signal count_2_DYMUX : STD_LOGIC; 
  signal count_2_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal count_2_F : STD_LOGIC; 
  signal count_2_CYMUXFAST : STD_LOGIC; 
  signal count_2_CYAND : STD_LOGIC; 
  signal count_2_FASTCARRY : STD_LOGIC; 
  signal count_2_CYMUXG2 : STD_LOGIC; 
  signal count_2_CYMUXF2 : STD_LOGIC; 
  signal count_2_LOGIC_ZERO : STD_LOGIC; 
  signal count_2_G : STD_LOGIC; 
  signal count_2_SRINV : STD_LOGIC; 
  signal count_2_CLKINV : STD_LOGIC; 
  signal count_2_CEINV : STD_LOGIC; 
  signal count_4_DXMUX : STD_LOGIC; 
  signal count_4_XORF : STD_LOGIC; 
  signal count_4_CYINIT : STD_LOGIC; 
  signal count_4_DYMUX : STD_LOGIC; 
  signal count_4_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal count_4_F : STD_LOGIC; 
  signal count_4_CYMUXFAST : STD_LOGIC; 
  signal count_4_CYAND : STD_LOGIC; 
  signal count_4_FASTCARRY : STD_LOGIC; 
  signal count_4_CYMUXG2 : STD_LOGIC; 
  signal count_4_CYMUXF2 : STD_LOGIC; 
  signal count_4_LOGIC_ZERO : STD_LOGIC; 
  signal count_4_G : STD_LOGIC; 
  signal count_4_SRINV : STD_LOGIC; 
  signal count_4_CLKINV : STD_LOGIC; 
  signal count_4_CEINV : STD_LOGIC; 
  signal count_6_DXMUX : STD_LOGIC; 
  signal count_6_XORF : STD_LOGIC; 
  signal count_6_CYINIT : STD_LOGIC; 
  signal count_6_DYMUX : STD_LOGIC; 
  signal count_6_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal count_6_F : STD_LOGIC; 
  signal count_6_CYMUXFAST : STD_LOGIC; 
  signal count_6_CYAND : STD_LOGIC; 
  signal count_6_FASTCARRY : STD_LOGIC; 
  signal count_6_CYMUXG2 : STD_LOGIC; 
  signal count_6_CYMUXF2 : STD_LOGIC; 
  signal count_6_LOGIC_ZERO : STD_LOGIC; 
  signal count_6_G : STD_LOGIC; 
  signal count_6_SRINV : STD_LOGIC; 
  signal count_6_CLKINV : STD_LOGIC; 
  signal count_6_CEINV : STD_LOGIC; 
  signal count_8_DXMUX : STD_LOGIC; 
  signal count_8_XORF : STD_LOGIC; 
  signal count_8_LOGIC_ZERO : STD_LOGIC; 
  signal count_8_CYINIT : STD_LOGIC; 
  signal count_8_F : STD_LOGIC; 
  signal count_8_DYMUX : STD_LOGIC; 
  signal count_8_XORG : STD_LOGIC; 
  signal count_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal count_9_rt : STD_LOGIC; 
  signal count_8_SRINV : STD_LOGIC; 
  signal count_8_CLKINV : STD_LOGIC; 
  signal count_8_CEINV : STD_LOGIC; 
  signal do_ENABLE : STD_LOGIC; 
  signal data_0_ENABLE : STD_LOGIC; 
  signal f2_FFY_RST : STD_LOGIC; 
  signal f2_FFX_RST : STD_LOGIC; 
  signal data_1_FFX_RST : STD_LOGIC; 
  signal c_FFd8_FFY_RST : STD_LOGIC; 
  signal c_FFd8_FFX_RST : STD_LOGIC; 
  signal data_2_FFX_RST : STD_LOGIC; 
  signal c_FFd10_FFY_RST : STD_LOGIC; 
  signal c_FFd10_FFX_SET : STD_LOGIC; 
  signal f1_FFY_RST : STD_LOGIC; 
  signal data_6_FFX_RST : STD_LOGIC; 
  signal data_7_FFX_RST : STD_LOGIC; 
  signal c_FFd2_FFY_RST : STD_LOGIC; 
  signal c_FFd2_FFX_RST : STD_LOGIC; 
  signal c_FFd4_FFY_RST : STD_LOGIC; 
  signal c_FFd4_FFX_RST : STD_LOGIC; 
  signal c_FFd6_FFY_RST : STD_LOGIC; 
  signal c_FFd6_FFX_RST : STD_LOGIC; 
  signal data_3_FFX_RST : STD_LOGIC; 
  signal data_4_FFX_RST : STD_LOGIC; 
  signal data_5_FFX_RST : STD_LOGIC; 
  signal PWR_GND_0_GND : STD_LOGIC; 
  signal PWR_GND_0_VCC : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal count : STD_LOGIC_VECTOR ( 9 downto 0 ); 
begin
  clk_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_INBUF_B,
      O => clk_BUFGP_IBUFG
    );
  clk_BUFGP_IBUFG_0 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk,
      O => clk_INBUF_B
    );
  clk_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => clk_ENABLE
    );
  data_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_1,
      CTL => data_1_ENABLE,
      O => data(1)
    );
  data_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_1_ENABLE
    );
  data_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_2,
      CTL => data_2_ENABLE,
      O => data(2)
    );
  data_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_2_ENABLE
    );
  data_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_3,
      CTL => data_3_ENABLE,
      O => data(3)
    );
  data_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_3_ENABLE
    );
  data_4_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_4,
      CTL => data_4_ENABLE,
      O => data(4)
    );
  data_4_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_4_ENABLE
    );
  data_5_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_5,
      CTL => data_5_ENABLE,
      O => data(5)
    );
  data_5_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_5_ENABLE
    );
  data_6_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_6,
      CTL => data_6_ENABLE,
      O => data(6)
    );
  data_6_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_6_ENABLE
    );
  data_7_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_7,
      CTL => data_7_ENABLE,
      O => data(7)
    );
  data_7_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => data_7_ENABLE
    );
  RXD_INBUF_USED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => RXD_INBUF_B,
      O => RXD_BUFGP_IBUFG
    );
  RXD_BUFGP_IBUFG_1 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => RXD,
      O => RXD_INBUF_B
    );
  RXD_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => RXD_ENABLE
    );
  N1292_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => N1292_F,
      O => N1292
    );
  N1292_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => N1292_G,
      O => Ker1290_SW0_O
    );
  do_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => do_OBUF_F,
      O => CHOICE639
    );
  do_OBUF_DYMUX_2 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n00171_O,
      O => do_OBUF_DYMUX
    );
  do_OBUF_SRINV_3 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f1_N95,
      O => do_OBUF_SRINV
    );
  do_OBUF_CLKINV_4 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => do_OBUF_CLKINV
    );
  clkdiv1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv1_F,
      O => f3
    );
  clkdiv1_DYMUX_5 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv1_BYINVNOT,
      O => clkdiv1_DYMUX
    );
  clkdiv1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv1_G,
      O => f1_N95
    );
  clkdiv1_BYINV : X_INV
    port map (
      I => clkdiv,
      O => clkdiv1_BYINVNOT
    );
  clkdiv1_SRINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f1_N95,
      O => clkdiv1_SRINV
    );
  clkdiv1_CLKINV_7 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clk_BUFGP,
      O => clkdiv1_CLKINV
    );
  clkdiv1_CEINV_8 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0013,
      O => clkdiv1_CEINV
    );
  Q_n001322 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => count(0),
      ADR1 => count(1),
      ADR2 => count(8),
      ADR3 => count(9),
      O => Q_n0013_G
    );
  Q_n0013_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0013_F,
      O => Q_n0013
    );
  Q_n0013_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0013_G,
      O => CHOICE661
    );
  Q_n0016_SW16 : X_LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      ADR0 => data_0,
      ADR1 => N1266,
      ADR2 => CHOICE594,
      ADR3 => c_FFd1,
      O => Q_n0016_SW16_O
    );
  f2_DXMUX_9 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n00251_O,
      O => f2_DXMUX
    );
  f2_DYMUX_10 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0016_SW16_O,
      O => f2_DYMUX
    );
  f2_CLKINV_11 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => f2_CLKINV
    );
  f2_CEINV_12 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => f2_CEINV
    );
  data_1_DXMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n001833_O,
      O => data_1_DXMUX
    );
  data_1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => data_1_G,
      O => Q_n001812_O
    );
  data_1_CLKINV_14 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => clkdiv,
      O => data_1_CLKINV
    );
  data_1_CEINV_15 : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => f3,
      O => data_1_CEINV
    );
  Ker1285 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => c_FFd8,
      ADR1 => c_FFd10,
      ADR2 => CHOICE635,
      ADR3 => c_FFd7,
      O => N1266_G
    );
  N1266_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => N1266_F,
      O => N1266
    );
  N1266_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => N1266_G,
      O => N1287
    );
  Q_n00138 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => count(2),
      ADR1 => count(3),
      ADR2 => count(5),
      ADR3 => count(4),
      O => Q_n0015_G
    );
  Q_n0015_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps
    )
    port map (
      I => Q_n0015_F,
      O => Q_n0015
    );
  Q_n0015_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 396 ps