new_top.syr

自己在ISE下用VHDL写的UART

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block new_top, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : new_top.ngr
Top Level Output File Name         : new_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Macro Statistics :
# Registers                        : 27
#      1-bit register              : 23
#      10-bit register             : 2
#      8-bit register              : 2
# Adders/Subtractors               : 2
#      10-bit adder                : 2

Cell Usage :
# BELS                             : 119
#      GND                         : 1
#      LUT1                        : 25
#      LUT2                        : 15
#      LUT2_D                      : 2
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT3_L                      : 2
#      LUT4                        : 10
#      LUT4_D                      : 3
#      LUT4_L                      : 15
#      MUXCY                       : 18
#      VCC                         : 1
#      XORCY                       : 18
# FlipFlops/Latches                : 79
#      FD                          : 2
#      FDC                         : 4
#      FDCE                        : 8
#      FDE                         : 41
#      FDE_1                       : 1
#      FDR                         : 12
#      FDRE                        : 11
# Clock Buffers                    : 3
#      BUFG                        : 1
#      BUFGP                       : 2
# IO Buffers                       : 3
#      IBUF                        : 1
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vlx25sf363-10 

 Number of Slices:                      56  out of  10752     0%  
 Number of Slice Flip Flops:            79  out of  21504     0%  
 Number of 4 input LUTs:                81  out of  21504     0%  
 Number of bonded IOBs:                  3  out of    242     1%  
 Number of GCLKs:                        3  out of     32     9%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_2_clkdiv:Q                    | NONE                   | 13    |
clk100m                            | BUFGP                  | 36    |
XLXI_1_clkdiv:Q                    | BUFG                   | 20    |
rxd                                | BUFGP                  | 1     |
XLXI_3_t3:Q                        | NONE                   | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 4.430ns (Maximum Frequency: 225.749MHz)
   Minimum input arrival time before clock: 2.684ns
   Maximum output required time after clock: 3.951ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_clkdiv:Q'
Delay:               3.285ns (Levels of Logic = 1)
  Source:            XLXI_2_flag2 (FF)
  Destination:       XLXI_2_busy (FF)
  Source Clock:      XLXI_2_clkdiv:Q rising
  Destination Clock: XLXI_2_clkdiv:Q rising

  Data Path: XLXI_2_flag2 to XLXI_2_busy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.358   0.618  XLXI_2_flag2 (XLXI_2_flag2)
     LUT2_D:I0->O          1   0.426   0.541  XLXI_2_busy_N3021 (XLXI_2_busy_N302)
     FDR:R                     1.343          XLXI_2_busy
    ----------------------------------------
    Total                      3.285ns (2.127ns logic, 1.158ns route)
                                       (64.7% logic, 35.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk100m'
Delay:               4.430ns (Levels of Logic = 2)
  Source:            XLXI_1_count_6 (FF)
  Destination:       XLXI_1_count_9 (FF)
  Source Clock:      clk100m rising
  Destination Clock: clk100m rising

  Data Path: XLXI_1_count_6 to XLXI_1_count_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.358   0.618  XLXI_1_count_6 (XLXI_1_count_6)
     LUT2:I0->O            1   0.426   0.540  XLXI_1__n001311 (CHOICE698)
     LUT4:I1->O           10   0.373   0.772  XLXI_1__n00151 (XLXI_1__n0015)
     FDRE:R                    1.343          XLXI_1_count_0
    ----------------------------------------
    Total                      4.430ns (2.500ns logic, 1.930ns route)
                                       (56.4% logic, 43.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_1_clkdiv:Q'
Delay:               3.888ns (Levels of Logic = 4)
  Source:            XLXI_1_c_FFd6 (FF)
  Destination:       XLXI_1_f2 (FF)
  Source Clock:      XLXI_1_clkdiv:Q rising
  Destination Clock: XLXI_1_clkdiv:Q rising

  Data Path: XLXI_1_c_FFd6 to XLXI_1_f2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.358   0.673  XLXI_1_c_FFd6 (XLXI_1_c_FFd6)
     LUT3:I0->O            2   0.426   0.604  XLXI_1_Ker2104_SW0 (CHOICE627)
     LUT4_D:I3->LO         1   0.208   0.100  XLXI_1_Ker2104 (N7526)
     LUT3:I0->O            3   0.426   0.618  XLXI_1_Ker20831 (XLXI_1_N2085)
     LUT4_L:I3->LO         1   0.208   0.000  XLXI_1__n00251 (XLXI_1__n0025)
     FDE:D                     0.268          XLXI_1_f2
    ----------------------------------------
    Total                      3.888ns (1.894ns logic, 1.994ns route)
                                       (48.7% logic, 51.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'rxd'
Delay:               2.002ns (Levels of Logic = 1)
  Source:            XLXI_1_f1 (FF)
  Destination:       XLXI_1_f1 (FF)
  Source Clock:      rxd falling
  Destination Clock: rxd falling

  Data Path: XLXI_1_f1 to XLXI_1_f1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            3   0.307   0.618  XLXI_1_f1 (XLXI_1_f1)
     LUT2_D:I1->LO         2   0.373   0.100  XLXI_1_f1_N2921 (N7532)
     FDE_1:CE                  0.604          XLXI_1_f1
    ----------------------------------------
    Total                      2.002ns (1.284ns logic, 0.718ns route)
                                       (64.2% logic, 35.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_t3:Q'
Delay:               2.053ns (Levels of Logic = 1)
  Source:            XLXI_2_flag1 (FF)
  Destination:       XLXI_2_flag1 (FF)
  Source Clock:      XLXI_3_t3:Q rising
  Destination Clock: XLXI_3_t3:Q rising

  Data Path: XLXI_2_flag1 to XLXI_2_flag1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.358   0.618  XLXI_2_flag1 (XLXI_2_flag1)
     LUT2_D:I1->LO         9   0.373   0.100  XLXI_2_busy_N3021 (N7524)
     FDE:CE                    0.604          XLXI_2_flag1
    ----------------------------------------
    Total                      2.053ns (1.335ns logic, 0.718ns route)
                                       (65.0% logic, 35.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1_clkdiv:Q'
Offset:              2.684ns (Levels of Logic = 3)
  Source:            rxd (PAD)
  Destination:       XLXI_1_data_5 (FF)
  Destination Clock: XLXI_1_clkdiv:Q rising

  Data Path: rxd to XLXI_1_data_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           10   0.305   0.772  rxd_BUFGP (rxd_BUFGP)
     LUT2:I1->O            1   0.373   0.540  XLXI_1__n0016_SW10 (CHOICE594)
     LUT4_L:I0->LO         1   0.426   0.000  XLXI_1__n0016_SW16 (XLXI_1__n0016)
     FDE:D                     0.268          XLXI_1_data_0
    ----------------------------------------
    Total                      2.684ns (1.372ns logic, 1.312ns route)
                                       (51.1% logic, 48.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_clkdiv:Q'
Offset:              3.951ns (Levels of Logic = 1)
  Source:            XLXI_2_busy (FF)
  Destination:       busy (PAD)
  Source Clock:      XLXI_2_clkdiv:Q rising

  Data Path: XLXI_2_busy to busy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.358   0.540  XLXI_2_busy (XLXI_2_busy)
     OBUF:I->O                 3.053          busy_OBUF (busy)
    ----------------------------------------
    Total                      3.951ns (3.411ns logic, 0.540ns route)
                                       (86.3% logic, 13.7% route)

=========================================================================
CPU : 35.14 / 37.18 s | Elapsed : 35.00 / 37.00 s
 
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Total memory usage is 126336 kilobytes