receive.syr

自己在ISE下用VHDL写的UART

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: receive.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : receive.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : receive
Output Format                      : NGC
Target Device                      : xc4vlx25-10-sf363

---- Source Options
Top Module Name                    : receive
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Map on DSP48                       : auto
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : receive.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/sk/iseobject/ex/sk/receive.vhd in Library work.
Architecture behavioral of Entity receive is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <receive> (Architecture <behavioral>).
Entity <receive> analyzed. Unit <receive> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <receive>.
    Related source file is E:/sk/iseobject/ex/sk/receive.vhd.
WARNING:Xst:653 - Signal <f4> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <f5> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <f6> is assigned but never used.
    Found finite state machine <FSM_0> for signal <c>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 10                                             |
    | Clock              | clkdiv (rising_edge)                           |
    | Clock enable       | f3 (positive)                                  |
    | Power Up State     | 0000000001                                     |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <data>.
    Found 1-bit register for signal <do>.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <count>.
    Found 1-bit register for signal <f1>.
    Found 1-bit register for signal <f2>.
    Found 1-bit xor2 for signal <f3>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
Unit <receive> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Counters                         : 1
 10-bit up counter                 : 1
# Registers                        : 22
 1-bit register                    : 22
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <receive> ...
Loading device for application Xst from file '4vlx25.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block receive, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : receive.ngr
Top Level Output File Name         : receive
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 11

Macro Statistics :
# Registers                        : 13
#      1-bit register              : 12
#      10-bit register             : 1
# Adders/Subtractors               : 1
#      10-bit adder                : 1

Cell Usage :
# BELS                             : 70
#      GND                         : 1
#      LUT1                        : 12
#      LUT2                        : 11
#      LUT2_D                      : 1
#      LUT3                        : 7
#      LUT3_L                      : 1
#      LUT4                        : 4
#      LUT4_D                      : 3
#      LUT4_L                      : 11
#      MUXCY                       : 9
#      VCC                         : 1
#      XORCY                       : 9
# FlipFlops/Latches                : 32
#      FDE                         : 19
#      FDE_1                       : 1
#      FDR                         : 1
#      FDRE                        : 11
# Clock Buffers                    : 3
#      BUFG                        : 1
#      BUFGP                       : 2
# IO Buffers                       : 9
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vlx25sf363-10 

 Number of Slices:                      28  out of  10752     0%  
 Number of Slice Flip Flops:            32  out of  21504     0%  
 Number of 4 input LUTs:                50  out of  21504     0%  
 Number of bonded IOBs:                  9  out of    242     3%  
 Number of GCLKs:                        3  out of     32     9%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkdiv:Q                           | BUFG                   | 20    |
RXD                                | BUFGP                  | 1     |
clk                                | BUFGP                  | 11    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 4.430ns (Maximum Frequency: 225.749MHz)
   Minimum input arrival time before clock: 2.684ns
   Maximum output required time after clock: 4.015ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkdiv:Q'
Delay:               3.888ns (Levels of Logic = 4)
  Source:            c_FFd6 (FF)
  Destination:       f2 (FF)
  Source Clock:      clkdiv:Q rising
  Destination Clock: clkdiv:Q rising

  Data Path: c_FFd6 to f2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              6   0.358   0.673  c_FFd6 (c_FFd6)
     LUT3:I0->O            2   0.426   0.604  Ker1285_SW0 (CHOICE635)
     LUT4_D:I3->LO         1   0.208   0.100  Ker1285 (N5620)
     LUT3:I0->O            3   0.426   0.618  Ker12641 (N1266)
     LUT4_L:I3->LO         1   0.208   0.000  _n00251 (_n0025)
     FDE:D                     0.268          f2
    ----------------------------------------
    Total                      3.888ns (1.894ns logic, 1.994ns route)
                                       (48.7% logic, 51.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'RXD'
Delay:               2.002ns (Levels of Logic = 1)
  Source:            f1 (FF)
  Destination:       f1 (FF)
  Source Clock:      RXD falling
  Destination Clock: RXD falling

  Data Path: f1 to f1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            3   0.307   0.618  f1 (f1)
     LUT2_D:I1->LO         2   0.373   0.100  f1_N951 (N5618)
     FDE_1:CE                  0.604          f1
    ----------------------------------------
    Total                      2.002ns (1.284ns logic, 0.718ns route)
                                       (64.2% logic, 35.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.430ns (Levels of Logic = 2)
  Source:            count_7 (FF)
  Destination:       count_9 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_7 to count_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.358   0.618  count_7 (count_7)
     LUT2:I0->O            1   0.426   0.540  _n001311 (CHOICE656)
     LUT4:I1->O           10   0.373   0.772  _n00151 (_n0015)
     FDRE:R                    1.343          count_0
    ----------------------------------------
    Total                      4.430ns (2.500ns logic, 1.930ns route)
                                       (56.4% logic, 43.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkdiv:Q'
Offset:              2.684ns (Levels of Logic = 3)
  Source:            RXD (PAD)
  Destination:       data_5 (FF)
  Destination Clock: clkdiv:Q rising

  Data Path: RXD to data_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           10   0.305   0.772  RXD_BUFGP (RXD_BUFGP)
     LUT2:I1->O            1   0.373   0.540  _n00240 (CHOICE603)
     LUT4_L:I0->LO         1   0.426   0.000  _n002413 (_n0024)
     FDE:D                     0.268          data_7
    ----------------------------------------
    Total                      2.684ns (1.372ns logic, 1.312ns route)
                                       (51.1% logic, 48.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv:Q'
Offset:              4.015ns (Levels of Logic = 1)
  Source:            do (FF)
  Destination:       do (PAD)
  Source Clock:      clkdiv:Q rising

  Data Path: do to do
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.358   0.604  do (do_OBUF)
     OBUF:I->O                 3.053          do_OBUF (do)
    ----------------------------------------
    Total                      4.015ns (3.411ns logic, 0.604ns route)
                                       (85.0% logic, 15.0% route)

=========================================================================
CPU : 33.00 / 35.16 s | Elapsed : 33.00 / 35.00 s
 
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Total memory usage is 124864 kilobytes