send.twr

自己在ISE下用VHDL写的UART

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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml send send.ncd -o
send.twr send.pcf


Design file:              send.ncd
Physical constraint file: send.pcf
Device,speed:             xc4vlx25,-10 (PREVIEW 1.46 2004-07-09)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock load
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data<0>     |    2.444(R)|    0.813(R)|load_BUFGP        |   0.000|
data<1>     |    2.442(R)|    0.815(R)|load_BUFGP        |   0.000|
data<2>     |    2.444(R)|    0.813(R)|load_BUFGP        |   0.000|
data<3>     |    2.442(R)|    0.815(R)|load_BUFGP        |   0.000|
data<4>     |    2.445(R)|    0.811(R)|load_BUFGP        |   0.000|
data<5>     |    2.437(R)|    0.823(R)|load_BUFGP        |   0.000|
data<6>     |    2.431(R)|    0.830(R)|load_BUFGP        |   0.000|
data<7>     |    2.439(R)|    0.820(R)|load_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.593|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock load
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
load           |    5.354|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Apr 12 14:58:34 2006
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Peak Memory Usage: 115 MB