new_top.par

自己在ISE下用VHDL写的UART

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

NEU-96YK9Y816SD::  Wed Apr 12 15:33:14 2006


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 new_top_map.ncd
new_top.ncd new_top.pcf 


Constraints file: new_top.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "new_top_map.ncd".
   "new_top" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10
Loading device for application Par from file '4vlx25.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.46 2004-07-09.


Resolved that IOB <clk100m> must be placed at site A8.
Resolved that IOB <rxd> must be placed at site E7.
Resolved that IOB <rst> must be placed at site U6.
Resolved that IOB <txd> must be placed at site D6.


Device utilization summary:

   Number of External IOBs             5 out of 240     2%
      Number of LOCed External IOBs    4 out of 5      80%

   Number of OLOGICs                   2 out of 448     1%
   Number of Slices                   63 out of 10752   1%

   Number of BUFGs                     3 out of 32      9%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897ba) REAL time: 8 secs 

......
WARNING:Place - A clock IOB  clock component is not placed at an optimal clock
   IOB site  The clock IOB component <rxd> is placed at site E7. The clock IO
   site can use the fast path between the IO and the Clock buffer/GCLK if the
   IOB is placed in the master Clock IOB Site. You may want to analyze why this
   problem exists and correct it. This is not an error so processing will
   continue.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 9 secs 

Phase 5.8
..
Phase 5.8 (Checksum:99858f) REAL time: 9 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 10 secs 

Writing design to file new_top.ncd.

Total REAL time to Placer completion: 10 secs 
Total CPU time to Placer completion: 9 secs 


Phase 1: 365 unrouted;       REAL time: 11 secs 

Phase 2: 328 unrouted;       REAL time: 19 secs 

Phase 3: 78 unrouted;       REAL time: 19 secs 

Phase 4: 0 unrouted;       REAL time: 19 secs 

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 17 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         rxd_BUFGP       |BUFGCTRL_X| No   |   10 |  0.000     |  1.894      |
+-------------------------+----------+------+------+------------+-------------+
|     clk100m_BUFGP       |BUFGCTRL_X| No   |   20 |  0.511     |  1.940      |
+-------------------------+----------+------+------+------------+-------------+
|     XLXI_1_clkdiv       |BUFGCTRL_X| No   |   15 |  0.485     |  1.890      |
+-------------------------+----------+------+------+------------+-------------+
|     XLXI_2_clkdiv       |   Local  |      |    9 |  1.024     |  1.865      |
+-------------------------+----------+------+------+------------+-------------+
|         XLXI_3_t3       |   Local  |      |    5 |  0.284     |  0.940      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 118


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.802
   The MAXIMUM PIN DELAY IS:                               3.757
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.898

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         297          51          12           5           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 21 secs 
Total CPU time to PAR completion: 18 secs 

Peak Memory Usage:  126 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file new_top.ncd.


PAR done.