dividefre4.vhd

四位十进制数码显示、量程自动转换的数字频率计。

--分频模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity dividefre4 is
	port(
		cp_20m:in std_logic;
		cp1:out std_logic;--200Hz片选信号
		cp2:out std_logic;--25Hz防抖动电路周期信号
		cp3:out std_logic);--5Hz闸门信号
end dividefre4;
architecture behavior of dividefre4 is
signal tout:integer range 0 to 50000;
signal tout1:integer range 0 to 7;
signal tout2:integer range 0 to 39;
signal cp:std_logic;
signal cp_1:std_logic;
signal cp_2:std_logic;
signal cp_3:std_logic;
begin
	process(cp_20m)--30000分频，分到400Hz
		begin
			if(cp_20m 'event and cp_20m='1')then
				if tout=29999 then
					tout<=0;
				else tout<=tout+1;
				end if;
				if tout=14999 then
					cp<='0';
				else cp<='1';
				end if;
			end if;
		end process;
	process(cp)--200Hz
		begin
			if(cp 'event and cp='1')then
				cp_1<=not cp_1;
			end if;
		end process;
	process(cp_1)
		begin
			if(cp_1 'event and cp_1='1')then
				if tout1=7 then tout1<=0;
				else tout1<=tout1+1;
				end if;
				if tout1=3 then
				cp_2<='1';
				elsif tout1=7 then cp_2<='0';
				end if;
				if tout2=39 then tout2<=0;
				else tout2<=tout2+1;
				end if;
				if tout2=39 then cp_3<='1';
					elsif tout2=19 then cp_3<='0';
				end if;
			end if;
		end process;
		cp1<=cp_1;cp2<=cp_2;cp3<=cp_3;
	end behavior;