display.vhd

四位十进制数码显示、量程自动转换的数字频率计。

--显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity display is
	port(
		cp1:in std_logic;--20Hz信号
		low:in std_logic;--输入小于10kHz的信号
		overflow:in std_logic;--输入大于9999kHz的信号
		p0,p1,p2,p3:in integer range 0 to 9;--输入信号
		show_1:out std_logic_vector(6 downto 0);
		show_2:out std_logic_vector(6 downto 0);
		show_3:out std_logic_vector(6 downto 0);
		show_4:out std_logic_vector(6 downto 0);--7位数码管输出信号
		sel:out std_logic_vector(3 downto 0));--片选信号
end display;
architecture behavior of display is
signal count:integer range 0 to 3;
signal sel_1:std_logic_vector(3 downto 0);
begin
	process(cp1)
		begin
			if(cp1 'event and cp1='1')then
				if count=3 then count<=0;
				else count<=count+1;
				end if;
			end if;
		end process;
	process(count)
		begin
			case count is
				when 0=>sel_1<="1110";
				when 1=>sel_1<="1101";
				when 2=>sel_1<="1011";
				when 3=>sel_1<="0111";
			end case;
	end process;
	process(low,overflow,sel_1,p0,p1,p2,p3)
		begin
			show_1<="1111110";--输出全'0'
			show_2<="1111110";
			show_3<="1111110";
			show_4<="1111110";
			if(low='1')then
				show_1<="1111110";--输入小于6kHz的信号时，输出全'0'
				show_2<="1111110";
				show_3<="1111110";
				show_4<="1111110";
			elsif(overflow='1')then
				show_1<="0110111";--输入大于4999kHz的信号时，输出全'H'
				show_2<="0110111";
				show_3<="0110111";
				show_4<="0110111";
			elsif(sel_1(0)='0')then
				case p0 is
					when 0=>show_1<="1111110";
					when 1=>show_1<="0110000";
					when 2=>show_1<="1101101";
					when 3=>show_1<="1111001";
					when 4=>show_1<="0110011";
					when 5=>show_1<="1011011";
					when 6=>show_1<="0011111";
					when 7=>show_1<="1110000";
					when 8=>show_1<="1111111";
					when 9=>show_1<="1110011";
				end case;
			elsif(sel_1(1)='0')then
				case p1 is
					when 0=>show_2<="1111110";
					when 1=>show_2<="0110000";
					when 2=>show_2<="1101101";
					when 3=>show_2<="1111001";
					when 4=>show_2<="0110011";
					when 5=>show_2<="1011011";
					when 6=>show_2<="0011111";
					when 7=>show_2<="1110000";
					when 8=>show_2<="1111111";
					when 9=>show_2<="1110011";
				end case;
			elsif(sel_1(2)='0')then
				case p2 is
					when 0=>show_3<="1111110";
					when 1=>show_3<="0110000";
					when 2=>show_3<="1101101";
					when 3=>show_3<="1111001";
					when 4=>show_3<="0110011";
					when 5=>show_3<="1011011";
					when 6=>show_3<="0011111";
					when 7=>show_3<="1110000";
					when 8=>show_3<="1111111";
					when 9=>show_3<="1110011";
				end case;
			elsif(sel_1(3)='0')then
				case p3 is
				when 0=>show_4<="1111110";
					when 1=>show_4<="0110000";
					when 2=>show_4<="1101101";
					when 3=>show_4<="1111001";
					when 4=>show_4<="0110011";
					when 5=>show_4<="1011011";
					when 6=>show_4<="0011111";
					when 7=>show_4<="1110000";
					when 8=>show_4<="1111111";
					when 9=>show_4<="1110011";
				end case;
			end if;
		end process;
		sel<=sel_1;
	end behavior;