fretest.vhd

四位十进制数码显示、量程自动转换的数字频率计。

--计数模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity fretest is
	port(
		enable:in std_logic;--开关信号，'1'有效
		cp3:in std_logic;--闸门信号
		input:in std_logic;--被测信号
		reset:in std_logic;--复位信号，'0'有效
		overflow:out std_logic;--输入大于9999kHz信号的输出
		low:out std_logic;--输入小于10kHz信号的输出
		play0,play1,play2,play3:out integer range 0 to 9;--4位BCD显示结果输出
		decimal:out std_logic_vector(2 downto 0));--小数点输出
	end fretest;
	architecture behavior of fretest is
		signal r0_1,r1_1,r2_1,r3_1,r4_1,r5_1:integer range 0 to 9;
		begin
			process(input,enable,reset)
				begin
					if enable='0' then null;
					elsif(input 'event and input='1')then
						if reset='1' then--复位信号为1时输出为全0
							overflow<='0';
							r0_1<=0;
							r1_1<=0;
							r2_1<=0;
							r3_1<=0;
							r4_1<=0;
							r5_1<=0;
						elsif cp3='0' then--当闸门处于低电平'1'时,输出为全0
							overflow<='0';
							r0_1<=0;
							r1_1<=0;
							r2_1<=0;
							r3_1<=0;
							r4_1<=0;
							r5_1<=0;
						else
							r0_1<=r0_1+1;
							if r0_1=9 then 
								r1_1<=r1_1+1;
								r0_1<=0;
								if (r1_1=9)then
									r2_1<=r2_1+1;
									r1_1<=0;
									if(r2_1=9)then
										r3_1<=r3_1+1;
										r2_1<=0;
										if(r3_1=9)then
											r4_1<=r4_1+1;
											r3_1<=0;
											if(r4_1=9)then
												r5_1<=r5_1+1;
												r4_1<=0;
												if(r5_1=9)then--当计到第六位仍不够时，溢出为'1'
													r5_1<=0;
													overflow<='1';
												end if;
											end if;
										end if;
									end if;
								end if;
							end if;
							if(r5_1=0 and r4_1=0 and r3_1=0)then
								low<='1';
							else low<='0';
							end if;
						end if;
					end if;
				end process;
			process(r5_1,r4_1,r0_1,r1_1,r2_1,r3_1)
				begin
					if r5_1=0 and r4_1=0 then--输出为##.##kHz
						play0<=r0_1;
						play1<=r1_1;
						play2<=r2_1;
						play3<=r3_1;
						decimal<="100";
					elsif r5_1=0 and r4_1>1 then
						play0<=r1_1;
						play1<=r2_1;
						play2<=r3_1;
						play3<=r4_1;
						decimal<="010";
					else
						play0<=r2_1;
						play1<=r3_1;
						play2<=r4_1;
						play3<=r5_1;
						decimal<="000";
					end if;
				end process;
		end behavior;