andmen.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 15 行

library ieee ;
use ieee.std_logic_1164.all ;

entity andmen is
port(in1,in2,in3,in4:in	std_logic;
outp:out   std_logic
);
end andmen;
architecture behv of andmen is
begin
outp<=in1 and in2 and in3 and in4;
end behv;