mux_8.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 31 行

library ieee ;
use ieee.std_logic_1164.all ;

entity mux_8 is
port(D7,D6,D5,D4,D3,D2,D1,D0:in	std_logic;
D,C,B:in	std_logic;
Y:out   std_logic
);
end mux_8 ;
architecture behv of mux_8 is
	signal sel:std_logic_vector(2 downto 0);
begin
sel<=D&C&B;
process(sel)
begin
case sel is
when "000" => Y<=D0;
when "001" => Y<=D1;
when "010" => Y<=D2;
when "011" => Y<=D3;
when "100" => Y<=D4;
when "101" => Y<=D5;
when "110" => Y<=D6;
when "111" => Y<=D7;
when others => Y<='0';
end case;
end process;
end behv;